starfive_vic7100_evb.dts 20 KB

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  1. /dts-v1/;
  2. #include "starfive_vic7100_clk.dtsi"
  3. #include <dt-bindings/starfive_fb.h>
  4. / {
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. compatible = "sifive,freedom-u74-arty";
  8. model = "sifive,freedom-u74-arty";
  9. chosen {
  10. linux,initrd-start = <0x0 0x86100000>;
  11. linux,initrd-end = <0x0 0x8c000000>;
  12. stdout-path = "/soc/serial@12440000:115200";
  13. #bootargs = "debug console=ttyS0 rootwait";
  14. };
  15. aliases {
  16. spi0="/soc/qspi@11860000";
  17. mshc0="/soc/sdio0@10000000";
  18. usb0="/soc/usb@104c0000";
  19. };
  20. cpus: cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. timebase-frequency = <6250000>;
  24. compatible = "starfive,fu74-g000";
  25. cpu@0 {
  26. clock-frequency = <0>;
  27. compatible = "starfive,rocket0", "riscv";
  28. d-cache-block-size = <64>;
  29. d-cache-sets = <64>;
  30. d-cache-size = <32768>;
  31. d-tlb-sets = <1>;
  32. d-tlb-size = <32>;
  33. device_type = "cpu";
  34. i-cache-block-size = <64>;
  35. i-cache-sets = <64>;
  36. i-cache-size = <32768>;
  37. i-tlb-sets = <1>;
  38. i-tlb-size = <32>;
  39. mmu-type = "riscv,sv39";
  40. next-level-cache = <&cachectrl>;
  41. reg = <0>;
  42. riscv,isa = "rv64imafdc";
  43. starfive,itim = <&itim0>;
  44. status = "okay";
  45. tlb-split;
  46. cpu0intctrl: interrupt-controller {
  47. #interrupt-cells = <1>;
  48. compatible = "riscv,cpu-intc";
  49. interrupt-controller;
  50. };
  51. };
  52. cpu@1 {
  53. clock-frequency = <0>;
  54. compatible = "starfive,rocket0", "riscv";
  55. d-cache-block-size = <64>;
  56. d-cache-sets = <64>;
  57. d-cache-size = <32768>;
  58. d-tlb-sets = <1>;
  59. d-tlb-size = <32>;
  60. device_type = "cpu";
  61. i-cache-block-size = <64>;
  62. i-cache-sets = <64>;
  63. i-cache-size = <32768>;
  64. i-tlb-sets = <1>;
  65. i-tlb-size = <32>;
  66. mmu-type = "riscv,sv39";
  67. next-level-cache = <&cachectrl>;
  68. reg = <1>;
  69. riscv,isa = "rv64imafdc";
  70. starfive,itim = <&itim1>;
  71. status = "okay";
  72. tlb-split;
  73. cpu1intctrl: interrupt-controller {
  74. #interrupt-cells = <1>;
  75. compatible = "riscv,cpu-intc";
  76. interrupt-controller;
  77. };
  78. };
  79. };
  80. memory@80000000 {
  81. device_type = "memory";
  82. reg = <0x0 0x80000000 0x2 0x0>;
  83. };
  84. memory@3000000000 {
  85. device_type = "memory";
  86. reg = <0x30 0x0 0x0 0x0>;
  87. };
  88. reserved-memory {
  89. #address-cells = <2>;
  90. #size-cells = <2>;
  91. ranges;
  92. linux,cma {
  93. compatible = "shared-dma-pool";
  94. reusable;
  95. size = <0x0 0x28000000>;
  96. alignment = <0x0 0x1000>;
  97. alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
  98. linux,cma-default;
  99. };
  100. jpu_reserved: framebuffer@c9000000 {
  101. reg = <0x0 0xc9000000 0x0 0x2000000>;
  102. };
  103. nvdla_reserved:framebuffer@d0000000{
  104. reg = <0x0 0xd0000000 0x0 0x28000000>;
  105. };
  106. vin_reserved: framebuffer@f9000000 {
  107. compatible = "shared-dma-pool";
  108. no-map;
  109. reg = <0x0 0xf9000000 0x0 0x1000000>;
  110. };
  111. sffb_reserved: framebuffer@fb000000 {
  112. compatible = "shared-dma-pool";
  113. no-map;
  114. reg = <0x0 0xfb000000 0x0 0x2000000>;
  115. };
  116. };
  117. soc {
  118. #address-cells = <2>;
  119. #size-cells = <2>;
  120. #clock-cells = <1>;
  121. compatible = "starfive,freedom-u74-arty", "simple-bus";
  122. ranges;
  123. cachectrl: cache-controller@2010000 {
  124. cache-block-size = <64>;
  125. cache-level = <2>;
  126. cache-sets = <2048>;
  127. cache-size = <2097152>;
  128. cache-unified;
  129. compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
  130. interrupt-parent = <&plic>;
  131. interrupts = <1 2 3>;
  132. /*next-level-cache = <&L40 &L36>;*/
  133. reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
  134. reg-names = "control", "sideband";
  135. };
  136. dtim: dtim@1000000 {
  137. compatible = "starfive,dtim0";
  138. reg = <0x0 0x1000000 0x0 0x2000>;
  139. reg-names = "mem";
  140. };
  141. itim0: itim@1808000 {
  142. compatible = "starfive,itim0";
  143. reg = <0x0 0x1808000 0x0 0x8000>;
  144. reg-names = "mem";
  145. };
  146. itim1: itim@1820000 {
  147. compatible = "starfive,itim0";
  148. reg = <0x0 0x1820000 0x0 0x8000>;
  149. reg-names = "mem";
  150. };
  151. clint: clint@2000000 {
  152. #interrupt-cells = <1>;
  153. compatible = "riscv,clint0";
  154. interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;
  155. reg = <0x0 0x2000000 0x0 0x10000>;
  156. reg-names = "control";
  157. };
  158. plic: plic@c000000 {
  159. #interrupt-cells = <1>;
  160. compatible = "riscv,plic0";
  161. interrupt-controller;
  162. interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;
  163. reg = <0x0 0xc000000 0x0 0x4000000>;
  164. reg-names = "control";
  165. riscv,max-priority = <7>;
  166. riscv,ndev = <127>;
  167. };
  168. uart3: serial@12440000 {
  169. compatible = "snps,dw-apb-uart";
  170. interrupt-parent = <&plic>;
  171. interrupts = <73>;
  172. reg = <0x0 0x12440000 0x0 0x10000>;
  173. reg-io-width = <4>;
  174. reg-shift = <2>;
  175. clocks = <&uartclk>, <&apb2clk>;
  176. clock-names = "baudclk", "apb_pclk";
  177. current-clock = <100000000>;
  178. current-speed = <115200>;
  179. status = "okay";
  180. };
  181. uart2: serial@12430000 {
  182. compatible = "snps,dw-apb-uart";
  183. interrupt-parent = <&plic>;
  184. interrupts = <72>;
  185. reg = <0x0 0x12430000 0x0 0x10000>;
  186. reg-io-width = <4>;
  187. reg-shift = <2>;
  188. clocks = <&uartclk>, <&apb2clk>;
  189. clock-names = "baudclk", "apb_pclk";
  190. current-clock = <100000000>;
  191. current-speed = <115200>;
  192. status = "disabled";
  193. };
  194. uart1: hs_serial@11880000 {
  195. compatible = "snps,dw-apb-uart";
  196. interrupt-parent = <&plic>;
  197. interrupts = <93>;
  198. reg = <0x0 0x11880000 0x0 0x10000>;
  199. reg-io-width = <4>;
  200. reg-shift = <2>;
  201. clocks = <&hs_uartclk>, <&apb1clk>;
  202. clock-names = "baudclk","apb_pclk";
  203. current-clock = <74250000>;
  204. current-speed = <115200>;
  205. status = "okay";
  206. };
  207. uart0: hs_serial@11870000 {
  208. compatible = "snps,dw-apb-uart";
  209. interrupt-parent = <&plic>;
  210. interrupts = <92>;
  211. reg = <0x0 0x11870000 0x0 0x10000>;
  212. reg-io-width = <4>;
  213. reg-shift = <2>;
  214. clocks = <&hs_uartclk>, <&apb1clk>;
  215. clock-names = "baudclk", "apb_pclk";
  216. current-clock = <74250000>;
  217. current-speed = <115200>;
  218. status = "okay";
  219. };
  220. dma2p: sgdma2p@100b0000 {
  221. compatible = "snps,axi-dma-1.01a";
  222. reg = <0x0 0x100b0000 0x0 0x10000>;
  223. clocks = <&axiclk>,<&ahb0clk>;
  224. clock-names = "core-clk", "cfgr-clk";
  225. interrupt-parent = <&plic>;
  226. interrupts = <2>;
  227. dma-channels = <4>;
  228. snps,dma-masters = <1>;
  229. snps,data-width = <4>;
  230. snps,block-size = <4096 4096 4096 4096>;
  231. snps,priority = <0 1 2 3>;
  232. snps,axi-max-burst-len = <128>;
  233. status = "okay";
  234. };
  235. dma1p: sgdma1p@10500000 {
  236. compatible = "snps,axi-dma-1.01a";
  237. reg = <0x0 0x10500000 0x0 0x10000>;
  238. clocks = <&axiclk>,<&ahb0clk>;
  239. clock-names = "core-clk", "cfgr-clk";
  240. interrupt-parent = <&plic>;
  241. interrupts = <1>;
  242. dma-channels = <16>;
  243. snps,dma-masters = <1>;
  244. snps,data-width = <3>;
  245. snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
  246. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  247. snps,axi-max-burst-len = <64>;
  248. status = "okay";
  249. };
  250. USB30: usb@104c0000 {
  251. compatible = "cdns,usb3";
  252. reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
  253. <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
  254. <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
  255. reg-names = "otg", "xhci", "dev";
  256. interrupt-parent = <&plic>;
  257. interrupts = <43>, <44>, <52>;
  258. interrupt-names = "otg",
  259. "host",
  260. "peripheral";
  261. phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
  262. status = "okay";
  263. };
  264. gpio: gpio@11910000 {
  265. compatible = "starfive,gpio0";
  266. interrupt-parent = <&plic>;
  267. interrupts = <32>;
  268. reg = <0x0 0x11910000 0x0 0x10000>;
  269. reg-names = "control";
  270. interrupt-controller;
  271. #gpio-cells = <2>;
  272. };
  273. i2c0: i2c@118b0000 {
  274. #address-cells = <1>;
  275. #size-cells = <0>;
  276. compatible = "snps,designware-i2c";
  277. reg = <0x0 0x118b0000 0x0 0x10000>;
  278. interrupt-parent = <&plic>;
  279. interrupts = <96>;
  280. /*clocks = <&hfclk>; */
  281. clock-frequency = <100000>;
  282. i2c-sda-hold-time-ns = <300>;
  283. i2c-sda-falling-time-ns = <3000>;
  284. i2c-scl-falling-time-ns = <3000>;
  285. auto_calc_scl_lhcnt;
  286. scl-gpio = <&gpio 62 0>;
  287. sda-gpio = <&gpio 61 0>;
  288. tda998x@70 {
  289. compatible = "nxp,tda998x";
  290. reg = <0x70>;
  291. };
  292. imx219@10 {
  293. compatible = "imx219";
  294. reg = <0x10>;
  295. reset-gpio = <&gpio 58 0>;
  296. };
  297. };
  298. i2c1: i2c@118c0000 {
  299. #address-cells = <1>;
  300. #size-cells = <0>;
  301. compatible = "snps,designware-i2c";
  302. reg = <0x0 0x118c0000 0x0 0x10000>;
  303. interrupt-parent = <&plic>;
  304. interrupts = <97>;
  305. clocks = <49500000>;
  306. clock-frequency = <400000>;
  307. i2c-sda-hold-time-ns = <300>;
  308. i2c-sda-falling-time-ns = <100>;
  309. i2c-scl-falling-time-ns = <100>;
  310. ac108_a: ac108@3b {
  311. compatible = "x-power,ac108_0";
  312. reg = <0x3b>;
  313. #sound-dai-cells = <0>;
  314. data-protocol = <0>;
  315. };
  316. wm8960: codec@1a {
  317. compatible = "wlf,wm8960";
  318. reg = <0x1a>;
  319. #sound-dai-cells = <0>;
  320. wlf,shared-lrclk;
  321. };
  322. };
  323. i2c2: i2c@12450000 {
  324. #address-cells = <1>;
  325. #size-cells = <0>;
  326. compatible = "snps,designware-i2c";
  327. reg = <0x0 0x12450000 0x0 0x10000>;
  328. interrupt-parent = <&plic>;
  329. interrupts = <74>;
  330. clocks = <50000000>;
  331. clock-frequency = <100000>;
  332. i2c-sda-hold-time-ns = <300>;
  333. i2c-sda-falling-time-ns = <500>;
  334. i2c-scl-falling-time-ns = <500>;
  335. auto_calc_scl_lhcnt;
  336. scl-gpio = <&gpio 18 0>;
  337. sda-gpio = <&gpio 19 0>;
  338. seeed_plane_i2c@45 {
  339. compatible = "seeed_panel";
  340. reg = <0x45>;
  341. };
  342. };
  343. trng: trng@118d0000 {
  344. compatible = "starfive,vic-rng";
  345. reg = <0x0 0x118d0000 0x0 0x10000>;
  346. interrupt-parent = <&plic>;
  347. interrupts = <98>;
  348. clocks = <&hfclk>;
  349. };
  350. crypto: crypto@100d0000 {
  351. compatible = "starfive,vic-sec";
  352. reg = <0x0 0x100d0000 0x0 0x20000>;
  353. interrupt-parent = <&plic>;
  354. interrupts = <31>;
  355. clocks = <&hfclk>;
  356. };
  357. /*gmac device configuration*/
  358. stmmac_axi_setup: stmmac-axi-config {
  359. snps,wr_osr_lmt = <0xf>;
  360. snps,rd_osr_lmt = <0xf>;
  361. snps,blen = <256 128 64 32 0 0 0>;
  362. };
  363. gmac:gmac@10020000{
  364. compatible = "snps,dwmac";
  365. reg = <0x0 0x10020000 0x0 0x10000>;
  366. interrupt-parent = <&plic>;
  367. interrupts = <6 7>;
  368. interrupt-names = "macirq","eth_wake_irq";
  369. max-frame-size = <9000>;
  370. phy-mode = "rgmii-txid";
  371. snps,multicast-filter-bins = <256>;
  372. snps,perfect-filter-entries = <128>;
  373. rx-fifo-depth = <32768>;
  374. tx-fifo-depth = <16384>;
  375. clocks = <&gmacclk>;
  376. clock-names = "stmmaceth";
  377. snps,fixed-burst = <1>;
  378. snps,no-pbl-x8 = <1>;
  379. /*snps,force_sf_dma_mode;*/
  380. snps,force_thresh_dma_mode;
  381. snps,axi-config = <&stmmac_axi_setup>;
  382. };
  383. nbdla: nvdla@0x11940000 {
  384. compatible = "nvidia,nvdla_os_initial";
  385. interrupt-parent = <&plic>;
  386. interrupts = <22>;
  387. memory-region = <&nvdla_reserved>;
  388. reg = <0x0 0x11940000 0x0 0x40000>;
  389. status = "okay";
  390. };
  391. jpu:coadj12@11900000 {
  392. compatible = "cm,codaj12-jpu-1";
  393. reg = <0x0 0x11900000 0x0 0x300>;
  394. memory-region = <&jpu_reserved>;
  395. interrupt-parent = <&plic>;
  396. interrupts = <24>;
  397. clocks = <&jpuclk>;
  398. clock-names = "jpege";
  399. reg-names = "control";
  400. status = "okay";
  401. };
  402. vpu_dec:vpu_dec@118F0000 {
  403. compatible = "c&m,cm511-vpu";
  404. reg = <0 0x118F0000 0 0x10000>;
  405. //memory-region = <&vpu_reserved>;
  406. interrupt-parent = <&plic>;
  407. interrupts = <23>;
  408. clocks = <&vpuclk>;
  409. clock-names = "vcodec";
  410. status = "okay";
  411. };
  412. vpu_enc:vpu_enc@118E0000 {
  413. compatible = "cm,cm521-vpu";
  414. reg = <0x0 0x118E0000 0x0 0x4000>;
  415. interrupt-parent = <&plic>;
  416. interrupts = <26>;
  417. clocks = <&vpuclk>;
  418. clock-names = "vcodec";
  419. reg-names = "control";
  420. };
  421. ptc: pwm@12490000 {
  422. compatible = "starfive,pwm0";
  423. reg = <0x0 0x12490000 0x0 0x10000>;
  424. reg-names = "control";
  425. sifive,approx-period = <100000000>;
  426. clocks = <&pwmclk>;
  427. #pwm-cells=<3>;
  428. sifive,npwm = <8>;
  429. };
  430. sfc_tmp:tmpsensor@124A0000 {
  431. compatible = "sfc,tempsensor";
  432. reg = <0x0 0x124A0000 0x0 0x1000>;
  433. interrupt-parent = <&plic>;
  434. interrupts = <122>;
  435. status = "okay";
  436. };
  437. qspi:qspi@11860000 {
  438. compatible = "cadence,qspi","cdns,qspi-nor";
  439. #address-cells = <1>;
  440. #size-cells = <0>;
  441. reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >;
  442. interrupts = <3>;
  443. interrupt-parent = <&plic>;
  444. clocks = <&qspi_clk>;
  445. cdns,fifo-depth = <256>;
  446. cdns,fifo-width = <4>;
  447. cdns,trigger-address = <0x00000000>;
  448. status = "okay";
  449. spi-max-frequency = <250000000>;
  450. nor_flash:nor-flash@0 {
  451. compatible = "spi-flash";
  452. reg=<0>;
  453. spi-max-frequency = <100000000>;
  454. page-size = <256>;
  455. block-size = <16>;
  456. cdns,read-delay = <4>;
  457. cdns,tshsl-ns = <1>;
  458. cdns,tsd2d-ns = <1>;
  459. cdns,tchsh-ns = <1>;
  460. cdns,tslch-ns = <1>;
  461. spi-tx-bus-width = <1>;
  462. spi-rx-bus-width = <1>;
  463. };
  464. };
  465. spi2:spi2@12410000 {
  466. compatible = "snps,dw-apb-ssi";
  467. #address-cells = <1>;
  468. #size-cells = <0>;
  469. interrupt-parent = <&plic>;
  470. interrupts = <70>;
  471. reg = <0x0 0x12410000 0x0 0x10000>;
  472. clocks = <&spiclk>;
  473. /*num-cs = <1>;
  474. cs-gpios = <&gpio 0 0>;*/
  475. spi_dev0: spi@0 {
  476. compatible = "rohm,dh2228fv";
  477. spi-max-frequency = <10000000>;
  478. reg = <0>;
  479. status = "okay";
  480. };
  481. };
  482. xrp@0 {
  483. compatible = "cdns,xrp";
  484. reg = <0x0 0xf0000000 0x0 0x01ffffff
  485. 0x10 0x72000000 0x0 0x00001000
  486. 0x10 0x72001000 0x0 0x00fff000
  487. 0x0 0x124b0000 0x0 0x00010000>;
  488. clocks = <&hfclk>;
  489. interrupt-parent = <&plic>;
  490. firmware-name = "vp6_elf";
  491. dsp-irq = <19 20>;
  492. dsp-irq-src = <0x20 0x21>;
  493. intc-irq-mode = <1>;
  494. intc-irq = <0 1>;
  495. interrupts = <27 28>;
  496. #address-cells = <1>;
  497. #size-cells = <1>;
  498. ranges = <0x40000000 0x0 0x40000000 0x01000000
  499. 0xb0000000 0x10 0x70000000 0x3000000>;
  500. dsp@0 {
  501. };
  502. };
  503. sdio0:sdio0@10000000{
  504. compatible = "snps,dw-mshc";
  505. reg = <0x0 0x10000000 0x0 0x10000>;
  506. interrupts = <4>;
  507. interrupt-parent = <&plic>;
  508. clocks = <&dwmmc_biuclk>;
  509. clock-names = "biu";
  510. clock-frequency = <100000000>;
  511. max-frequency = <50000000>;
  512. fifo-depth = <32>;
  513. card-detect-delay = <300>;
  514. fifo-watermark-aligned;
  515. data-addr = <0>;
  516. bus-width = <4>;
  517. cap-sd-highspeed;
  518. /*broken-cd;*/
  519. cap-sdio-irq;
  520. cap-mmc-hw-reset;
  521. non-removable;
  522. enable-sdio-wakeup;
  523. keep-power-in-suspend;
  524. /*cap-power-off-card;*/
  525. cap-mmc-highspeed;
  526. /*fixed-emmc-driver-type;*/
  527. post-power-on-delay-ms = <200>;
  528. };
  529. sdio1:sdio1@10010000{
  530. compatible = "snps,dw-mshc";
  531. reg = <0x0 0x10010000 0x0 0x10000>;
  532. interrupts = <5>;
  533. interrupt-parent = <&plic>;
  534. clocks = <&dwmmc_biuclk>;
  535. clock-names = "biu";
  536. clock-frequency = <100000000>;
  537. max-frequency = <26000000>;
  538. fifo-depth = <32>;
  539. card-detect-delay = <300>;
  540. fifo-watermark-aligned;
  541. data-addr = <0>;
  542. bus-width = <4>;
  543. cap-sd-highspeed;
  544. /*broken-cd;*/
  545. cap-sdio-irq;
  546. cap-mmc-hw-reset;
  547. non-removable;
  548. enable-sdio-wakeup;
  549. keep-power-in-suspend;
  550. /*cap-power-off-card;*/
  551. cap-mmc-highspeed;
  552. /*fixed-emmc-driver-type;*/
  553. post-power-on-delay-ms = <200>;
  554. };
  555. sfivefb:sfivefb@12000000 {
  556. compatible = "starfive,vpp-lcdc";
  557. interrupt-parent = <&plic>;
  558. interrupts = <101>, <103>;
  559. interrupt-names = "lcdc_irq", "vpp1_irq";
  560. reg = <0x0 0x12000000 0x0 0x10000>,
  561. <0x0 0x12100000 0x0 0x10000>,
  562. <0x0 0x12040000 0x0 0x10000>,
  563. <0x0 0x12080000 0x0 0x10000>,
  564. <0x0 0x120c0000 0x0 0x10000>,
  565. <0x0 0x12240000 0x0 0x10000>,
  566. <0x0 0x12250000 0x0 0x10000>,
  567. <0x0 0x12260000 0x0 0x10000>;
  568. reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
  569. memory-region = <&sffb_reserved>;
  570. clocks = <&uartclk>, <&apb2clk>;
  571. clock-names = "baudclk", "apb_pclk";
  572. status = "okay";
  573. ddr-format = <WIN_FMT_RGB565>;
  574. pp1 {
  575. pp-id = <1>;
  576. fifo-out;
  577. src-format = <COLOR_YUV420_NV21>;
  578. src-width = <1920>;
  579. src-height = <1080>;
  580. dst-format = <COLOR_RGB888_ARGB>;
  581. dst-width = <1920>;
  582. dst-height = <1080>;
  583. };
  584. };
  585. vin_sysctl:vin_sysctl@19800000 {
  586. compatible = "starfive,stf-vin";
  587. reg = <0x0 0x19800000 0x0 0x10000>,
  588. <0x0 0x19810000 0x0 0x10000>,
  589. <0x0 0x19820000 0x0 0x10000>,
  590. <0x0 0x19830000 0x0 0x10000>,
  591. <0x0 0x19840000 0x0 0x10000>,
  592. <0x0 0x19870000 0x0 0x30000>,
  593. <0x0 0x198a0000 0x0 0x30000>,
  594. <0x0 0x11800000 0x0 0x10000>,
  595. <0x0 0x11840000 0x0 0x10000>,
  596. <0x0 0x11858000 0x0 0x10000>;
  597. reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad";
  598. interrupt-parent = <&plic>;
  599. interrupts = <119 109>;
  600. memory-region = <&vin_reserved>;
  601. /*for imx219 vim&isp*/
  602. format = <SRC_CSI2RX_VIN_ISP>;
  603. frame-width = <1920>;
  604. frame-height =<1080>;
  605. /*defaule config sc2235
  606. format = <SRC_DVP_SENSOR_VIN_ISP>;
  607. frame-width = <1920>;
  608. frame-height =<1080>;
  609. isp0_enable;*/
  610. /*defaule config ov5640
  611. format = <SRC_DVP_SENSOR_VIN_OV5640>;
  612. frame-width = <1920>;
  613. frame-height =<1080>;*/
  614. /*defaule config for ov4689 vin&isp
  615. format = <SRC_CSI2RX_VIN_ISP>;
  616. frame-width = <800>;
  617. frame-height =<480>;
  618. */
  619. isp0_enable;
  620. csi-lane = <2>;
  621. csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
  622. csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
  623. csi-clane-swap = /bits/ 8 <0>;
  624. csi-clane-pn-swap = /bits/ 8 <0>;
  625. csi-mipiID = <0>;
  626. csi-width = <1920>;
  627. csi-height = <1080>;
  628. csi-dt = <0x2b>;
  629. };
  630. i2sadc0: i2sadc0@10400000 {
  631. compatible = "snps,designware-i2sadc0";
  632. reg = <0x0 0x10400000 0x0 0x1000>;
  633. interrupt-parent = <&plic>;
  634. interrupts = <59>;
  635. interrupt-names = "rx";
  636. clocks = <&apb1clk>;
  637. clock-names = "i2sclk";
  638. #sound-dai-cells = <0>;
  639. dmas = <&dma2p 28>;
  640. dma-names = "rx";
  641. };
  642. i2svad: i2svad@10420000 {
  643. compatible = "sf,sf-i2svad";
  644. reg = <0x0 0x10420000 0x0 0x1000> ;
  645. interrupt-parent = <&plic>;
  646. interrupts = <60>, <61>;
  647. interrupt-names = "spintr", "slintr";
  648. clocks = <&apb1clk>;
  649. clock-names = "i2sclk";
  650. #sound-dai-cells = <0>;
  651. };
  652. i2sdac0: i2sdac0@10450000 {
  653. compatible = "snps,designware-i2sdac0";
  654. reg = <0x0 0x10450000 0x0 0x1000>;
  655. interrupt-parent = <&plic>;
  656. interrupts = <64>;
  657. interrupt-names = "tx";
  658. clocks = <&apb1clk>;
  659. clock-names = "i2sclk";
  660. #sound-dai-cells = <0>;
  661. dmas = <&dma2p 30>;
  662. dma-names = "tx";
  663. };
  664. i2sdac1: i2sdac1@10460000 {
  665. compatible = "snps,designware-i2sdac1";
  666. reg = <0x0 0x10460000 0x0 0x1000>;
  667. interrupt-parent = <&plic>;
  668. interrupts = <66>;
  669. interrupt-names = "tx";
  670. clocks = <&apb1clk>;
  671. clock-names = "i2sclk";
  672. #sound-dai-cells = <0>;
  673. dmas = <&dma2p 31>;
  674. dma-names = "tx";
  675. };
  676. i2sdac16k: i2sdac16k@10470000 {
  677. compatible = "snps,designware-i2sdac16k";
  678. reg = <0x0 0x10470000 0x0 0x1000>;
  679. interrupt-parent = <&plic>;
  680. interrupts = <68>;
  681. interrupt-names = "tx";
  682. clocks = <&apb1clk>;
  683. clock-names = "i2sclk";
  684. #sound-dai-cells = <0>;
  685. dmas = <&dma2p 29>;
  686. dma-names = "tx";
  687. };
  688. spdif0: spdif0@10430000 {
  689. compatible = "starfive,sf-spdif";
  690. reg = <0x0 0x10430000 0x0 0x1000>;
  691. interrupt-parent = <&plic>;
  692. interrupts = <62>;
  693. interrupt-names = "tx";
  694. clocks = <&audioclk>;
  695. clock-names = "audioclk";
  696. #sound-dai-cells = <0>;
  697. };
  698. pdm: pdm@10410000 {
  699. compatible = "starfive,sf-pdm";
  700. reg = <0x0 0x10410000 0x0 0x1000>, <0x0 0x10480000 0x0 0x1000>;
  701. reg-names = "pdm", "audio-clk";
  702. clocks = <&audioclk>;
  703. clock-names = "audioclk";
  704. #sound-dai-cells = <0>;
  705. };
  706. ac108_mclk: ac108_mclk {
  707. compatible = "fixed-clock";
  708. #clock-cells = <0>;
  709. clock-frequency = <24576000>;
  710. };
  711. wm8960_mclk: wm8960_mclk {
  712. compatible = "fixed-clock";
  713. #clock-cells = <0>;
  714. clock-frequency = <24576000>;
  715. };
  716. spdif_transmitter: spdif_transmitter {
  717. compatible = "linux,spdif-dit";
  718. #sound-dai-cells = <0>;
  719. };
  720. spdif_receiver: spdif_receiver {
  721. compatible = "linux,spdif-dir";
  722. #sound-dai-cells = <0>;
  723. };
  724. pwmdac: pwmdac@10440000 {
  725. compatible = "sf,pwmdac";
  726. reg = <0x0 0x10440000 0x0 0x1000>;
  727. clocks = <&apb1clk>;
  728. dmas = <&dma2p 23>;
  729. dma-names = "tx";
  730. #sound-dai-cells = <0>;
  731. };
  732. codec: pwmdac-transmitter {
  733. compatible = "linux,pwmdac-dit";
  734. #sound-dai-cells = <0>;
  735. };
  736. dmic_codec: dmic_codec {
  737. compatible = "dmic-codec";
  738. #sound-dai-cells = <0>;
  739. };
  740. sound:snd-card{
  741. compatible = "sf-audio-card";
  742. };
  743. };
  744. };
  745. #include "tda998x_1080p.dtsi"
  746. /* #include "codecs/sf_pdm.dtsi" */
  747. #include "codecs/sf_spdif.dtsi"
  748. /* #include "codecs/sf_ac108.dtsi" */
  749. /* #include "codecs/sf_wm8960.dtsi" */
  750. /* #include "codecs/sf_vad.dtsi" */