Kconfig 6.5 KB

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  1. menu "RISC-V architecture"
  2. depends on RISCV
  3. config SYS_ARCH
  4. default "riscv"
  5. choice
  6. prompt "Target select"
  7. optional
  8. config TARGET_AX25_AE350
  9. bool "Support ax25-ae350"
  10. config TARGET_MICROCHIP_ICICLE
  11. bool "Support Microchip PolarFire-SoC Icicle Board"
  12. config TARGET_QEMU_VIRT
  13. bool "Support QEMU Virt Board"
  14. config TARGET_SIFIVE_FU540
  15. bool "Support SiFive FU540 Board"
  16. config TARGET_STARFIVE_VIC7100
  17. bool "Support StarFive VIC7100 Board"
  18. config TARGET_SIPEED_MAIX
  19. bool "Support Sipeed Maix Board"
  20. endchoice
  21. choice
  22. prompt "Target VIC sub-board"
  23. default VIC_EVB_V1
  24. depends on TARGET_STARFIVE_VIC7100
  25. optional
  26. config VIC_STARLIGHT_V1
  27. bool "Support VIC Starlight V1."
  28. config VIC_EVB_V1
  29. bool "Support VIC EVB-V1."
  30. endchoice
  31. config SYS_ICACHE_OFF
  32. bool "Do not enable icache"
  33. default n
  34. help
  35. Do not enable instruction cache in U-Boot.
  36. config SPL_SYS_ICACHE_OFF
  37. bool "Do not enable icache in SPL"
  38. depends on SPL
  39. default SYS_ICACHE_OFF
  40. help
  41. Do not enable instruction cache in SPL.
  42. config SYS_DCACHE_OFF
  43. bool "Do not enable dcache"
  44. default n
  45. help
  46. Do not enable data cache in U-Boot.
  47. config SPL_SYS_DCACHE_OFF
  48. bool "Do not enable dcache in SPL"
  49. depends on SPL
  50. default SYS_DCACHE_OFF
  51. help
  52. Do not enable data cache in SPL.
  53. # board-specific options below
  54. source "board/AndesTech/ax25-ae350/Kconfig"
  55. source "board/emulation/qemu-riscv/Kconfig"
  56. source "board/microchip/mpfs_icicle/Kconfig"
  57. source "board/sifive/fu540/Kconfig"
  58. source "board/starfive/vic7100/Kconfig"
  59. source "board/sipeed/maix/Kconfig"
  60. # platform-specific options below
  61. source "arch/riscv/cpu/ax25/Kconfig"
  62. source "arch/riscv/cpu/fu540/Kconfig"
  63. source "arch/riscv/cpu/generic/Kconfig"
  64. # architecture-specific options below
  65. choice
  66. prompt "Base ISA"
  67. default ARCH_RV32I
  68. config ARCH_RV32I
  69. bool "RV32I"
  70. select 32BIT
  71. help
  72. Choose this option to target the RV32I base integer instruction set.
  73. config ARCH_RV64I
  74. bool "RV64I"
  75. select 64BIT
  76. select PHYS_64BIT
  77. help
  78. Choose this option to target the RV64I base integer instruction set.
  79. endchoice
  80. choice
  81. prompt "Code Model"
  82. default CMODEL_MEDLOW
  83. config CMODEL_MEDLOW
  84. bool "medium low code model"
  85. help
  86. U-Boot and its statically defined symbols must lie within a single 2 GiB
  87. address range and must lie between absolute addresses -2 GiB and +2 GiB.
  88. config CMODEL_MEDANY
  89. bool "medium any code model"
  90. help
  91. U-Boot and its statically defined symbols must be within any single 2 GiB
  92. address range.
  93. endchoice
  94. choice
  95. prompt "Run Mode"
  96. default RISCV_MMODE
  97. config RISCV_MMODE
  98. bool "Machine"
  99. help
  100. Choose this option to build U-Boot for RISC-V M-Mode.
  101. config RISCV_SMODE
  102. bool "Supervisor"
  103. help
  104. Choose this option to build U-Boot for RISC-V S-Mode.
  105. endchoice
  106. choice
  107. prompt "SPL Run Mode"
  108. default SPL_RISCV_MMODE
  109. depends on SPL
  110. config SPL_RISCV_MMODE
  111. bool "Machine"
  112. help
  113. Choose this option to build U-Boot SPL for RISC-V M-Mode.
  114. config SPL_RISCV_SMODE
  115. bool "Supervisor"
  116. help
  117. Choose this option to build U-Boot SPL for RISC-V S-Mode.
  118. endchoice
  119. config RISCV_ISA_C
  120. bool "Emit compressed instructions"
  121. default y
  122. help
  123. Adds "C" to the ISA subsets that the toolchain is allowed to emit
  124. when building U-Boot, which results in compressed instructions in the
  125. U-Boot binary.
  126. config RISCV_ISA_A
  127. def_bool y
  128. config 32BIT
  129. bool
  130. config 64BIT
  131. bool
  132. config SIFIVE_CLINT
  133. bool
  134. depends on RISCV_MMODE || SPL_RISCV_MMODE
  135. help
  136. The SiFive CLINT block holds memory-mapped control and status registers
  137. associated with software and timer interrupts.
  138. config ANDES_PLIC
  139. bool
  140. depends on RISCV_MMODE || SPL_RISCV_MMODE
  141. select REGMAP
  142. select SYSCON
  143. select SPL_REGMAP if SPL
  144. select SPL_SYSCON if SPL
  145. help
  146. The Andes PLIC block holds memory-mapped claim and pending registers
  147. associated with software interrupt.
  148. config SYS_MALLOC_F_LEN
  149. default 0x1000
  150. config SMP
  151. bool "Symmetric Multi-Processing"
  152. depends on SBI_V01 || !RISCV_SMODE
  153. help
  154. This enables support for systems with more than one CPU. If
  155. you say N here, U-Boot will run on single and multiprocessor
  156. machines, but will use only one CPU of a multiprocessor
  157. machine. If you say Y here, U-Boot will run on many, but not
  158. all, single processor machines.
  159. config SPL_SMP
  160. bool "Symmetric Multi-Processing in SPL"
  161. depends on SPL && SPL_RISCV_MMODE
  162. default y
  163. help
  164. This enables support for systems with more than one CPU in SPL.
  165. If you say N here, U-Boot SPL will run on single and multiprocessor
  166. machines, but will use only one CPU of a multiprocessor
  167. machine. If you say Y here, U-Boot SPL will run on many, but not
  168. all, single processor machines.
  169. config NR_CPUS
  170. int "Maximum number of CPUs (2-32)"
  171. range 2 32
  172. depends on SMP || SPL_SMP
  173. default 8
  174. help
  175. On multiprocessor machines, U-Boot sets up a stack for each CPU.
  176. Stack memory is pre-allocated. U-Boot must therefore know the
  177. maximum number of CPUs that may be present.
  178. config SBI
  179. bool
  180. default y if RISCV_SMODE || SPL_RISCV_SMODE
  181. choice
  182. prompt "SBI support"
  183. default SBI_V02
  184. config SBI_V01
  185. bool "SBI v0.1 support"
  186. depends on SBI
  187. help
  188. This config allows kernel to use SBI v0.1 APIs. This will be
  189. deprecated in future once legacy M-mode software are no longer in use.
  190. config SBI_V02
  191. bool "SBI v0.2 support"
  192. depends on SBI
  193. help
  194. This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
  195. scalable and extendable to handle future needs for RISC-V supervisor
  196. interfaces. For example, with SBI v0.2 HSM extension, only a single
  197. hart need to boot and enter operating system. The booting hart can
  198. bring up secondary harts one by one afterwards.
  199. Choose this option if OpenSBI v0.7 or above release is used together
  200. with U-Boot.
  201. endchoice
  202. config SBI_IPI
  203. bool
  204. depends on SBI
  205. default y if RISCV_SMODE || SPL_RISCV_SMODE
  206. depends on SMP
  207. config XIP
  208. bool "XIP mode"
  209. help
  210. XIP (eXecute In Place) is a method for executing code directly
  211. from a NOR flash memory without copying the code to ram.
  212. Say yes here if U-Boot boots from flash directly.
  213. config SHOW_REGS
  214. bool "Show registers on unhandled exception"
  215. config RISCV_PRIV_1_9
  216. bool "Use version 1.9 of the RISC-V priviledged specification"
  217. help
  218. Older versions of the RISC-V priviledged specification had
  219. separate counter enable CSRs for each privilege mode. Writing
  220. to the unified mcounteren CSR on a processor implementing the
  221. old specification will result in an illegal instruction
  222. exception. In addition to counter CSR changes, the way virtual
  223. memory is configured was also changed.
  224. config STACK_SIZE_SHIFT
  225. int
  226. default 14
  227. config OF_BOARD_FIXUP
  228. default y if OF_SEPARATE && RISCV_SMODE
  229. endmenu