starfive_vic7100_evb.dts 13 KB

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  1. /dts-v1/;
  2. #include "starfive_vic7100_clk.dtsi"
  3. / {
  4. #address-cells = <2>;
  5. #size-cells = <2>;
  6. compatible = "sifive,freedom-u74-arty";
  7. model = "sifive,freedom-u74-arty";
  8. chosen {
  9. linux,initrd-start = <0x0 0x86100000>;
  10. linux,initrd-end = <0x0 0x8c000000>;
  11. stdout-path = "/soc/serial@12440000:115200";
  12. #bootargs = "debug console=ttyS0 rootwait";
  13. };
  14. aliases {
  15. spi0="/soc/qspi@11860000";
  16. mshc0="/soc/sdio0@10000000";
  17. usb0="/soc/usb@104c0000";
  18. };
  19. cpus: cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. timebase-frequency = <6250000>;
  23. compatible = "starfive,fu74-g000";
  24. cpu@0 {
  25. clock-frequency = <0>;
  26. compatible = "starfive,rocket0", "riscv";
  27. d-cache-block-size = <64>;
  28. d-cache-sets = <64>;
  29. d-cache-size = <32768>;
  30. d-tlb-sets = <1>;
  31. d-tlb-size = <32>;
  32. device_type = "cpu";
  33. i-cache-block-size = <64>;
  34. i-cache-sets = <64>;
  35. i-cache-size = <32768>;
  36. i-tlb-sets = <1>;
  37. i-tlb-size = <32>;
  38. mmu-type = "riscv,sv39";
  39. next-level-cache = <&cachectrl>;
  40. reg = <0>;
  41. riscv,isa = "rv64imafdc";
  42. starfive,itim = <&itim0>;
  43. status = "okay";
  44. tlb-split;
  45. cpu0intctrl: interrupt-controller {
  46. #interrupt-cells = <1>;
  47. compatible = "riscv,cpu-intc";
  48. interrupt-controller;
  49. };
  50. };
  51. cpu@1 {
  52. clock-frequency = <0>;
  53. compatible = "starfive,rocket0", "riscv";
  54. d-cache-block-size = <64>;
  55. d-cache-sets = <64>;
  56. d-cache-size = <32768>;
  57. d-tlb-sets = <1>;
  58. d-tlb-size = <32>;
  59. device_type = "cpu";
  60. i-cache-block-size = <64>;
  61. i-cache-sets = <64>;
  62. i-cache-size = <32768>;
  63. i-tlb-sets = <1>;
  64. i-tlb-size = <32>;
  65. mmu-type = "riscv,sv39";
  66. next-level-cache = <&cachectrl>;
  67. reg = <1>;
  68. riscv,isa = "rv64imafdc";
  69. starfive,itim = <&itim1>;
  70. status = "okay";
  71. tlb-split;
  72. cpu1intctrl: interrupt-controller {
  73. #interrupt-cells = <1>;
  74. compatible = "riscv,cpu-intc";
  75. interrupt-controller;
  76. };
  77. };
  78. };
  79. memory@80000000 {
  80. device_type = "memory";
  81. reg = <0x0 0x80000000 0x2 0x0>;
  82. };
  83. memory@3000000000 {
  84. device_type = "memory";
  85. reg = <0x30 0x0 0x0 0x0>;
  86. };
  87. reserved-memory {
  88. #address-cells = <2>;
  89. #size-cells = <2>;
  90. ranges;
  91. linux,cma {
  92. compatible = "shared-dma-pool";
  93. reusable;
  94. size = <0x0 0x28000000>;
  95. alignment = <0x0 0x1000>;
  96. alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
  97. linux,cma-default;
  98. };
  99. jpu_reserved: framebuffer@c9000000 {
  100. reg = <0x0 0xc9000000 0x0 0x2000000>;
  101. };
  102. nvdla_reserved:framebuffer@d0000000{
  103. reg = <0x0 0xd0000000 0x0 0x28000000>;
  104. };
  105. };
  106. soc {
  107. #address-cells = <2>;
  108. #size-cells = <2>;
  109. #clock-cells = <1>;
  110. compatible = "starfive,freedom-u74-arty", "simple-bus";
  111. ranges;
  112. cachectrl: cache-controller@2010000 {
  113. cache-block-size = <64>;
  114. cache-level = <2>;
  115. cache-sets = <2048>;
  116. cache-size = <2097152>;
  117. cache-unified;
  118. compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
  119. interrupt-parent = <&plic>;
  120. interrupts = <1 2 3>;
  121. /*next-level-cache = <&L40 &L36>;*/
  122. reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
  123. reg-names = "control", "sideband";
  124. };
  125. dtim: dtim@1000000 {
  126. compatible = "starfive,dtim0";
  127. reg = <0x0 0x1000000 0x0 0x2000>;
  128. reg-names = "mem";
  129. };
  130. itim0: itim@1808000 {
  131. compatible = "starfive,itim0";
  132. reg = <0x0 0x1808000 0x0 0x8000>;
  133. reg-names = "mem";
  134. };
  135. itim1: itim@1820000 {
  136. compatible = "starfive,itim0";
  137. reg = <0x0 0x1820000 0x0 0x8000>;
  138. reg-names = "mem";
  139. };
  140. clint: clint@2000000 {
  141. #interrupt-cells = <1>;
  142. compatible = "riscv,clint0";
  143. interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;
  144. reg = <0x0 0x2000000 0x0 0x10000>;
  145. reg-names = "control";
  146. };
  147. plic: plic@c000000 {
  148. #interrupt-cells = <1>;
  149. compatible = "riscv,plic0";
  150. interrupt-controller;
  151. interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;
  152. reg = <0x0 0xc000000 0x0 0x4000000>;
  153. reg-names = "control";
  154. riscv,max-priority = <7>;
  155. riscv,ndev = <127>;
  156. };
  157. uart3: serial@12440000 {
  158. compatible = "snps,dw-apb-uart";
  159. interrupt-parent = <&plic>;
  160. interrupts = <73>;
  161. reg = <0x0 0x12440000 0x0 0x10000>;
  162. reg-io-width = <4>;
  163. reg-shift = <2>;
  164. clocks = <&uartclk>, <&apb2clk>;
  165. clock-names = "baudclk", "apb_pclk";
  166. current-clock = <100000000>;
  167. current-speed = <115200>;
  168. status = "okay";
  169. };
  170. uart2: serial@12430000 {
  171. compatible = "snps,dw-apb-uart";
  172. interrupt-parent = <&plic>;
  173. interrupts = <72>;
  174. reg = <0x0 0x12430000 0x0 0x10000>;
  175. reg-io-width = <4>;
  176. reg-shift = <2>;
  177. clocks = <&uartclk>, <&apb2clk>;
  178. clock-names = "baudclk", "apb_pclk";
  179. current-clock = <100000000>;
  180. current-speed = <115200>;
  181. status = "disabled";
  182. };
  183. uart1: hs_serial@11880000 {
  184. compatible = "snps,dw-apb-uart";
  185. interrupt-parent = <&plic>;
  186. interrupts = <93>;
  187. reg = <0x0 0x11880000 0x0 0x10000>;
  188. reg-io-width = <4>;
  189. reg-shift = <2>;
  190. clocks = <&hs_uartclk>, <&apb1clk>;
  191. clock-names = "baudclk","apb_pclk";
  192. current-clock = <74250000>;
  193. current-speed = <115200>;
  194. status = "okay";
  195. };
  196. uart0: hs_serial@11870000 {
  197. compatible = "snps,dw-apb-uart";
  198. interrupt-parent = <&plic>;
  199. interrupts = <92>;
  200. reg = <0x0 0x11870000 0x0 0x10000>;
  201. reg-io-width = <4>;
  202. reg-shift = <2>;
  203. clocks = <&hs_uartclk>, <&apb1clk>;
  204. clock-names = "baudclk", "apb_pclk";
  205. current-clock = <74250000>;
  206. current-speed = <115200>;
  207. status = "okay";
  208. };
  209. dma2p: sgdma2p@100b0000 {
  210. compatible = "snps,axi-dma-1.01a";
  211. reg = <0x0 0x100b0000 0x0 0x10000>;
  212. clocks = <&axiclk>,<&ahb0clk>;
  213. clock-names = "core-clk", "cfgr-clk";
  214. interrupt-parent = <&plic>;
  215. interrupts = <2>;
  216. dma-channels = <4>;
  217. snps,dma-masters = <1>;
  218. snps,data-width = <4>;
  219. snps,block-size = <4096 4096 4096 4096>;
  220. snps,priority = <0 1 2 3>;
  221. snps,axi-max-burst-len = <128>;
  222. status = "okay";
  223. };
  224. dma1p: sgdma1p@10500000 {
  225. compatible = "snps,axi-dma-1.01a";
  226. reg = <0x0 0x10500000 0x0 0x10000>;
  227. clocks = <&axiclk>,<&ahb0clk>;
  228. clock-names = "core-clk", "cfgr-clk";
  229. interrupt-parent = <&plic>;
  230. interrupts = <1>;
  231. dma-channels = <16>;
  232. snps,dma-masters = <1>;
  233. snps,data-width = <3>;
  234. snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
  235. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  236. snps,axi-max-burst-len = <64>;
  237. status = "okay";
  238. };
  239. USB30: usb@104c0000 {
  240. compatible = "cdns,usb3";
  241. reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
  242. <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
  243. <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
  244. reg-names = "otg", "xhci", "dev";
  245. interrupt-parent = <&plic>;
  246. interrupts = <43>, <44>, <52>;
  247. interrupt-names = "otg",
  248. "host",
  249. "peripheral";
  250. phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
  251. status = "okay";
  252. };
  253. gpio: gpio@11910000 {
  254. compatible = "starfive,gpio0";
  255. interrupt-parent = <&plic>;
  256. interrupts = <32>;
  257. reg = <0x0 0x11910000 0x0 0x10000>;
  258. reg-names = "control";
  259. interrupt-controller;
  260. #gpio-cells = <2>;
  261. };
  262. i2c0: i2c@118b0000 {
  263. #address-cells = <1>;
  264. #size-cells = <0>;
  265. compatible = "snps,designware-i2c";
  266. reg = <0x0 0x118b0000 0x0 0x10000>;
  267. interrupt-parent = <&plic>;
  268. interrupts = <96>;
  269. /*clocks = <&hfclk>; */
  270. clock-frequency = <1000000>;
  271. i2c-sda-hold-time-ns = <300>;
  272. i2c-sda-falling-time-ns = <500>;
  273. i2c-scl-falling-time-ns = <500>;
  274. };
  275. i2c1: i2c@118c0000 {
  276. #address-cells = <1>;
  277. #size-cells = <0>;
  278. compatible = "snps,designware-i2c";
  279. reg = <0x0 0x118c0000 0x0 0x10000>;
  280. interrupt-parent = <&plic>;
  281. interrupts = <97>;
  282. clocks = <49500000>;
  283. clock-frequency = <400000>;
  284. i2c-sda-hold-time-ns = <300>;
  285. i2c-sda-falling-time-ns = <100>;
  286. i2c-scl-falling-time-ns = <100>;
  287. };
  288. i2c2: i2c@12450000 {
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. compatible = "snps,designware-i2c";
  292. reg = <0x0 0x12450000 0x0 0x10000>;
  293. interrupt-parent = <&plic>;
  294. interrupts = <74>;
  295. clocks = <50000000>;
  296. clock-frequency = <100000>;
  297. i2c-sda-hold-time-ns = <300>;
  298. i2c-sda-falling-time-ns = <500>;
  299. i2c-scl-falling-time-ns = <500>;
  300. seeed_plane_i2c@45 {
  301. compatible = "seeed_panel";
  302. reg = <0x45>;
  303. };
  304. };
  305. trng: trng@118d0000 {
  306. compatible = "starfive,vic-rng";
  307. reg = <0x0 0x118d0000 0x0 0x10000>;
  308. interrupt-parent = <&plic>;
  309. interrupts = <98>;
  310. clocks = <&hfclk>;
  311. };
  312. crypto: crypto@100d0000 {
  313. compatible = "starfive,vic-sec";
  314. reg = <0x0 0x100d0000 0x0 0x20000>;
  315. interrupt-parent = <&plic>;
  316. interrupts = <31>;
  317. clocks = <&hfclk>;
  318. };
  319. /*gmac device configuration*/
  320. stmmac_axi_setup: stmmac-axi-config {
  321. snps,wr_osr_lmt = <0xf>;
  322. snps,rd_osr_lmt = <0xf>;
  323. snps,blen = <256 128 64 32 0 0 0>;
  324. };
  325. gmac:gmac@10020000{
  326. compatible = "snps,dwmac";
  327. reg = <0x0 0x10020000 0x0 0x10000>;
  328. interrupt-parent = <&plic>;
  329. interrupts = <6 7>;
  330. interrupt-names = "macirq","eth_wake_irq";
  331. max-frame-size = <9000>;
  332. phy-mode = "rgmii-txid";
  333. snps,multicast-filter-bins = <256>;
  334. snps,perfect-filter-entries = <128>;
  335. rx-fifo-depth = <32768>;
  336. tx-fifo-depth = <16384>;
  337. clocks = <&gmacclk>;
  338. clock-names = "stmmaceth";
  339. snps,fixed-burst = <1>;
  340. snps,no-pbl-x8 = <1>;
  341. /*snps,force_sf_dma_mode;*/
  342. snps,force_thresh_dma_mode;
  343. snps,axi-config = <&stmmac_axi_setup>;
  344. };
  345. nbdla: nvdla@0x11940000 {
  346. compatible = "nvidia,nvdla_os_initial";
  347. interrupt-parent = <&plic>;
  348. interrupts = <22>;
  349. memory-region = <&nvdla_reserved>;
  350. reg = <0x0 0x11940000 0x0 0x40000>;
  351. status = "okay";
  352. };
  353. jpu:coadj12@11900000 {
  354. compatible = "cm,codaj12-jpu-1";
  355. reg = <0x0 0x11900000 0x0 0x300>;
  356. memory-region = <&jpu_reserved>;
  357. interrupt-parent = <&plic>;
  358. interrupts = <24>;
  359. clocks = <&jpuclk>;
  360. clock-names = "jpege";
  361. reg-names = "control";
  362. status = "okay";
  363. };
  364. vpu_dec:vpu_dec@118F0000 {
  365. compatible = "c&m,cm511-vpu";
  366. reg = <0 0x118F0000 0 0x10000>;
  367. //memory-region = <&vpu_reserved>;
  368. interrupt-parent = <&plic>;
  369. interrupts = <23>;
  370. clocks = <&vpuclk>;
  371. clock-names = "vcodec";
  372. status = "okay";
  373. };
  374. vpu_enc:vpu_enc@118E0000 {
  375. compatible = "cm,cm521-vpu";
  376. reg = <0x0 0x118E0000 0x0 0x4000>;
  377. interrupt-parent = <&plic>;
  378. interrupts = <26>;
  379. clocks = <&vpuclk>;
  380. clock-names = "vcodec";
  381. reg-names = "control";
  382. };
  383. ptc: pwm@12490000 {
  384. compatible = "starfive,pwm0";
  385. reg = <0x0 0x12490000 0x0 0x10000>;
  386. reg-names = "control";
  387. sifive,approx-period = <100000000>;
  388. clocks = <&pwmclk>;
  389. #pwm-cells=<3>;
  390. sifive,npwm = <8>;
  391. };
  392. qspi:qspi@11860000 {
  393. compatible = "cadence,qspi","cdns,qspi-nor";
  394. #address-cells = <1>;
  395. #size-cells = <0>;
  396. reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >;
  397. interrupts = <3>;
  398. interrupt-parent = <&plic>;
  399. clocks = <&qspi_clk>;
  400. cdns,fifo-depth = <256>;
  401. cdns,fifo-width = <4>;
  402. cdns,trigger-address = <0x00000000>;
  403. status = "okay";
  404. spi-max-frequency = <250000000>;
  405. nor_flash:nor-flash@0 {
  406. compatible = "spi-flash";
  407. reg=<0>;
  408. spi-max-frequency = <100000000>;
  409. page-size = <256>;
  410. block-size = <16>;
  411. cdns,read-delay = <4>;
  412. cdns,tshsl-ns = <1>;
  413. cdns,tsd2d-ns = <1>;
  414. cdns,tchsh-ns = <1>;
  415. cdns,tslch-ns = <1>;
  416. spi-tx-bus-width = <1>;
  417. spi-rx-bus-width = <1>;
  418. };
  419. };
  420. xrp@0 {
  421. compatible = "cdns,xrp";
  422. reg = <0x0 0xf0000000 0x0 0x01ffffff
  423. 0x10 0x72000000 0x0 0x00001000
  424. 0x10 0x72001000 0x0 0x00fff000
  425. 0x0 0x124b0000 0x0 0x00010000>;
  426. clocks = <&hfclk>;
  427. interrupt-parent = <&plic>;
  428. firmware-name = "vp6_elf";
  429. dsp-irq = <19 20>;
  430. dsp-irq-src = <0x20 0x21>;
  431. intc-irq-mode = <1>;
  432. intc-irq = <0 1>;
  433. interrupts = <27 28>;
  434. #address-cells = <1>;
  435. #size-cells = <1>;
  436. ranges = <0x40000000 0x0 0x40000000 0x01000000
  437. 0xb0000000 0x10 0x70000000 0x3000000>;
  438. dsp@0 {
  439. };
  440. };
  441. sdio0:sdio0@10000000{
  442. compatible = "snps,dw-mshc";
  443. reg = <0x0 0x10000000 0x0 0x10000>;
  444. interrupts = <4>;
  445. interrupt-parent = <&plic>;
  446. clocks = <&dwmmc_biuclk>;
  447. clock-names = "biu";
  448. clock-frequency = <100000000>;
  449. max-frequency = <50000000>;
  450. fifo-depth = <32>;
  451. card-detect-delay = <300>;
  452. fifo-watermark-aligned;
  453. data-addr = <0>;
  454. bus-width = <4>;
  455. cap-sd-highspeed;
  456. /*broken-cd;*/
  457. cap-sdio-irq;
  458. cap-mmc-hw-reset;
  459. non-removable;
  460. enable-sdio-wakeup;
  461. keep-power-in-suspend;
  462. /*cap-power-off-card;*/
  463. cap-mmc-highspeed;
  464. /*fixed-emmc-driver-type;*/
  465. post-power-on-delay-ms = <200>;
  466. };
  467. sdio1:sdio1@10010000{
  468. compatible = "snps,dw-mshc";
  469. reg = <0x0 0x10010000 0x0 0x10000>;
  470. interrupts = <5>;
  471. interrupt-parent = <&plic>;
  472. clocks = <&dwmmc_biuclk>;
  473. clock-names = "biu";
  474. clock-frequency = <100000000>;
  475. max-frequency = <26000000>;
  476. fifo-depth = <32>;
  477. card-detect-delay = <300>;
  478. fifo-watermark-aligned;
  479. data-addr = <0>;
  480. bus-width = <4>;
  481. cap-sd-highspeed;
  482. /*broken-cd;*/
  483. cap-sdio-irq;
  484. cap-mmc-hw-reset;
  485. non-removable;
  486. enable-sdio-wakeup;
  487. keep-power-in-suspend;
  488. /*cap-power-off-card;*/
  489. cap-mmc-highspeed;
  490. /*fixed-emmc-driver-type;*/
  491. post-power-on-delay-ms = <200>;
  492. };
  493. sfc_tmp:tmpsensor@124A0000 {
  494. compatible = "sfc,tempsensor";
  495. reg = <0x0 0x124A0000 0x0 0x1000>;
  496. interrupt-parent = <&plic>;
  497. interrupts = <122>;
  498. status = "okay";
  499. };
  500. };
  501. };