starfive_vic7100_evb.dts 20 KB

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  1. /dts-v1/;
  2. #include "starfive_vic7100_clk.dtsi"
  3. #include <dt-bindings/starfive_fb.h>
  4. / {
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. compatible = "sifive,freedom-u74-arty";
  8. model = "sifive,freedom-u74-arty";
  9. chosen {
  10. linux,initrd-start = <0x0 0x86100000>;
  11. linux,initrd-end = <0x0 0x8c000000>;
  12. stdout-path = "/soc/serial@12440000:115200";
  13. #bootargs = "debug console=ttyS0 rootwait";
  14. };
  15. aliases {
  16. spi0="/soc/qspi@11860000";
  17. mshc0="/soc/sdio0@10000000";
  18. usb0="/soc/usb@104c0000";
  19. };
  20. cpus: cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. timebase-frequency = <6250000>;
  24. compatible = "starfive,fu74-g000";
  25. cpu@0 {
  26. clock-frequency = <0>;
  27. compatible = "starfive,rocket0", "riscv";
  28. d-cache-block-size = <64>;
  29. d-cache-sets = <64>;
  30. d-cache-size = <32768>;
  31. d-tlb-sets = <1>;
  32. d-tlb-size = <32>;
  33. device_type = "cpu";
  34. i-cache-block-size = <64>;
  35. i-cache-sets = <64>;
  36. i-cache-size = <32768>;
  37. i-tlb-sets = <1>;
  38. i-tlb-size = <32>;
  39. mmu-type = "riscv,sv39";
  40. next-level-cache = <&cachectrl>;
  41. reg = <0>;
  42. riscv,isa = "rv64imafdc";
  43. starfive,itim = <&itim0>;
  44. status = "okay";
  45. tlb-split;
  46. cpu0intctrl: interrupt-controller {
  47. #interrupt-cells = <1>;
  48. compatible = "riscv,cpu-intc";
  49. interrupt-controller;
  50. };
  51. };
  52. cpu@1 {
  53. clock-frequency = <0>;
  54. compatible = "starfive,rocket0", "riscv";
  55. d-cache-block-size = <64>;
  56. d-cache-sets = <64>;
  57. d-cache-size = <32768>;
  58. d-tlb-sets = <1>;
  59. d-tlb-size = <32>;
  60. device_type = "cpu";
  61. i-cache-block-size = <64>;
  62. i-cache-sets = <64>;
  63. i-cache-size = <32768>;
  64. i-tlb-sets = <1>;
  65. i-tlb-size = <32>;
  66. mmu-type = "riscv,sv39";
  67. next-level-cache = <&cachectrl>;
  68. reg = <1>;
  69. riscv,isa = "rv64imafdc";
  70. starfive,itim = <&itim1>;
  71. status = "okay";
  72. tlb-split;
  73. cpu1intctrl: interrupt-controller {
  74. #interrupt-cells = <1>;
  75. compatible = "riscv,cpu-intc";
  76. interrupt-controller;
  77. };
  78. };
  79. };
  80. memory@80000000 {
  81. device_type = "memory";
  82. reg = <0x0 0x80000000 0x2 0x0>;
  83. };
  84. memory@3000000000 {
  85. device_type = "memory";
  86. reg = <0x30 0x0 0x0 0x0>;
  87. };
  88. reserved-memory {
  89. #address-cells = <2>;
  90. #size-cells = <2>;
  91. ranges;
  92. linux,cma {
  93. compatible = "shared-dma-pool";
  94. reusable;
  95. size = <0x0 0x28000000>;
  96. alignment = <0x0 0x1000>;
  97. alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
  98. linux,cma-default;
  99. };
  100. jpu_reserved: framebuffer@c9000000 {
  101. reg = <0x0 0xc9000000 0x0 0x2000000>;
  102. };
  103. nvdla_reserved:framebuffer@d0000000{
  104. reg = <0x0 0xd0000000 0x0 0x28000000>;
  105. };
  106. vin_reserved: framebuffer@f9000000 {
  107. compatible = "shared-dma-pool";
  108. no-map;
  109. reg = <0x0 0xf9000000 0x0 0x1000000>;
  110. };
  111. sffb_reserved: framebuffer@fb000000 {
  112. compatible = "shared-dma-pool";
  113. no-map;
  114. reg = <0x0 0xfb000000 0x0 0x2000000>;
  115. };
  116. };
  117. soc {
  118. #address-cells = <2>;
  119. #size-cells = <2>;
  120. #clock-cells = <1>;
  121. compatible = "starfive,freedom-u74-arty", "simple-bus";
  122. ranges;
  123. cachectrl: cache-controller@2010000 {
  124. cache-block-size = <64>;
  125. cache-level = <2>;
  126. cache-sets = <2048>;
  127. cache-size = <2097152>;
  128. cache-unified;
  129. compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
  130. interrupt-parent = <&plic>;
  131. interrupts = <1 2 3>;
  132. /*next-level-cache = <&L40 &L36>;*/
  133. reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
  134. reg-names = "control", "sideband";
  135. };
  136. dtim: dtim@1000000 {
  137. compatible = "starfive,dtim0";
  138. reg = <0x0 0x1000000 0x0 0x2000>;
  139. reg-names = "mem";
  140. };
  141. itim0: itim@1808000 {
  142. compatible = "starfive,itim0";
  143. reg = <0x0 0x1808000 0x0 0x8000>;
  144. reg-names = "mem";
  145. };
  146. itim1: itim@1820000 {
  147. compatible = "starfive,itim0";
  148. reg = <0x0 0x1820000 0x0 0x8000>;
  149. reg-names = "mem";
  150. };
  151. clint: clint@2000000 {
  152. #interrupt-cells = <1>;
  153. compatible = "riscv,clint0";
  154. interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;
  155. reg = <0x0 0x2000000 0x0 0x10000>;
  156. reg-names = "control";
  157. };
  158. plic: plic@c000000 {
  159. #interrupt-cells = <1>;
  160. compatible = "riscv,plic0";
  161. interrupt-controller;
  162. interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;
  163. reg = <0x0 0xc000000 0x0 0x4000000>;
  164. reg-names = "control";
  165. riscv,max-priority = <7>;
  166. riscv,ndev = <127>;
  167. };
  168. uart3: serial@12440000 {
  169. compatible = "snps,dw-apb-uart";
  170. interrupt-parent = <&plic>;
  171. interrupts = <73>;
  172. reg = <0x0 0x12440000 0x0 0x10000>;
  173. reg-io-width = <4>;
  174. reg-shift = <2>;
  175. clocks = <&uartclk>, <&apb2clk>;
  176. clock-names = "baudclk", "apb_pclk";
  177. current-clock = <100000000>;
  178. current-speed = <115200>;
  179. status = "okay";
  180. };
  181. uart2: serial@12430000 {
  182. compatible = "snps,dw-apb-uart";
  183. interrupt-parent = <&plic>;
  184. interrupts = <72>;
  185. reg = <0x0 0x12430000 0x0 0x10000>;
  186. reg-io-width = <4>;
  187. reg-shift = <2>;
  188. clocks = <&uartclk>, <&apb2clk>;
  189. clock-names = "baudclk", "apb_pclk";
  190. current-clock = <100000000>;
  191. current-speed = <115200>;
  192. status = "disabled";
  193. };
  194. uart1: hs_serial@11880000 {
  195. compatible = "snps,dw-apb-uart";
  196. interrupt-parent = <&plic>;
  197. interrupts = <93>;
  198. reg = <0x0 0x11880000 0x0 0x10000>;
  199. reg-io-width = <4>;
  200. reg-shift = <2>;
  201. clocks = <&hs_uartclk>, <&apb1clk>;
  202. clock-names = "baudclk","apb_pclk";
  203. current-clock = <74250000>;
  204. current-speed = <115200>;
  205. status = "okay";
  206. };
  207. uart0: hs_serial@11870000 {
  208. compatible = "snps,dw-apb-uart";
  209. interrupt-parent = <&plic>;
  210. interrupts = <92>;
  211. reg = <0x0 0x11870000 0x0 0x10000>;
  212. reg-io-width = <4>;
  213. reg-shift = <2>;
  214. clocks = <&hs_uartclk>, <&apb1clk>;
  215. clock-names = "baudclk", "apb_pclk";
  216. current-clock = <74250000>;
  217. current-speed = <115200>;
  218. status = "okay";
  219. };
  220. dma2p: sgdma2p@100b0000 {
  221. compatible = "snps,axi-dma-1.01a";
  222. reg = <0x0 0x100b0000 0x0 0x10000>;
  223. clocks = <&axiclk>,<&ahb0clk>;
  224. clock-names = "core-clk", "cfgr-clk";
  225. interrupt-parent = <&plic>;
  226. interrupts = <2>;
  227. #dma-cells = <1>;
  228. dma-channels = <4>;
  229. snps,dma-masters = <1>;
  230. snps,data-width = <4>;
  231. snps,block-size = <4096 4096 4096 4096>;
  232. snps,priority = <0 1 2 3>;
  233. snps,axi-max-burst-len = <128>;
  234. status = "okay";
  235. };
  236. dma1p: sgdma1p@10500000 {
  237. compatible = "snps,axi-dma-1.01a";
  238. reg = <0x0 0x10500000 0x0 0x10000>;
  239. clocks = <&axiclk>,<&ahb0clk>;
  240. clock-names = "core-clk", "cfgr-clk";
  241. interrupt-parent = <&plic>;
  242. interrupts = <1>;
  243. #dma-cells = <1>;
  244. dma-channels = <16>;
  245. snps,dma-masters = <1>;
  246. snps,data-width = <3>;
  247. snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
  248. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  249. snps,axi-max-burst-len = <64>;
  250. status = "okay";
  251. };
  252. USB30: usb@104c0000 {
  253. compatible = "cdns,usb3";
  254. reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
  255. <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
  256. <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
  257. reg-names = "otg", "xhci", "dev";
  258. interrupt-parent = <&plic>;
  259. interrupts = <43>, <44>, <52>;
  260. interrupt-names = "otg",
  261. "host",
  262. "peripheral";
  263. phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
  264. status = "okay";
  265. };
  266. gpio: gpio@11910000 {
  267. compatible = "starfive,gpio0";
  268. interrupt-parent = <&plic>;
  269. interrupts = <32>;
  270. reg = <0x0 0x11910000 0x0 0x10000>;
  271. reg-names = "control";
  272. interrupt-controller;
  273. #gpio-cells = <2>;
  274. };
  275. i2c0: i2c@118b0000 {
  276. #address-cells = <1>;
  277. #size-cells = <0>;
  278. compatible = "snps,designware-i2c";
  279. reg = <0x0 0x118b0000 0x0 0x10000>;
  280. interrupt-parent = <&plic>;
  281. interrupts = <96>;
  282. /*clocks = <&hfclk>; */
  283. clock-frequency = <100000>;
  284. i2c-sda-hold-time-ns = <300>;
  285. i2c-sda-falling-time-ns = <3000>;
  286. i2c-scl-falling-time-ns = <3000>;
  287. auto_calc_scl_lhcnt;
  288. scl-gpio = <&gpio 62 0>;
  289. sda-gpio = <&gpio 61 0>;
  290. tda998x@70 {
  291. compatible = "nxp,tda998x";
  292. reg = <0x70>;
  293. };
  294. imx219@10 {
  295. compatible = "imx219";
  296. reg = <0x10>;
  297. reset-gpio = <&gpio 58 0>;
  298. };
  299. };
  300. i2c1: i2c@118c0000 {
  301. #address-cells = <1>;
  302. #size-cells = <0>;
  303. compatible = "snps,designware-i2c";
  304. reg = <0x0 0x118c0000 0x0 0x10000>;
  305. interrupt-parent = <&plic>;
  306. interrupts = <97>;
  307. clocks = <49500000>;
  308. clock-frequency = <400000>;
  309. i2c-sda-hold-time-ns = <300>;
  310. i2c-sda-falling-time-ns = <100>;
  311. i2c-scl-falling-time-ns = <100>;
  312. ac108_a: ac108@3b {
  313. compatible = "x-power,ac108_0";
  314. reg = <0x3b>;
  315. #sound-dai-cells = <0>;
  316. data-protocol = <0>;
  317. };
  318. wm8960: codec@1a {
  319. compatible = "wlf,wm8960";
  320. reg = <0x1a>;
  321. #sound-dai-cells = <0>;
  322. wlf,shared-lrclk;
  323. };
  324. };
  325. i2c2: i2c@12450000 {
  326. #address-cells = <1>;
  327. #size-cells = <0>;
  328. compatible = "snps,designware-i2c";
  329. reg = <0x0 0x12450000 0x0 0x10000>;
  330. interrupt-parent = <&plic>;
  331. interrupts = <74>;
  332. clocks = <50000000>;
  333. clock-frequency = <100000>;
  334. i2c-sda-hold-time-ns = <300>;
  335. i2c-sda-falling-time-ns = <500>;
  336. i2c-scl-falling-time-ns = <500>;
  337. auto_calc_scl_lhcnt;
  338. scl-gpio = <&gpio 18 0>;
  339. sda-gpio = <&gpio 19 0>;
  340. seeed_plane_i2c@45 {
  341. compatible = "seeed_panel";
  342. reg = <0x45>;
  343. };
  344. };
  345. trng: trng@118d0000 {
  346. compatible = "starfive,vic-rng";
  347. reg = <0x0 0x118d0000 0x0 0x10000>;
  348. interrupt-parent = <&plic>;
  349. interrupts = <98>;
  350. clocks = <&hfclk>;
  351. };
  352. crypto: crypto@100d0000 {
  353. compatible = "starfive,vic-sec";
  354. reg = <0x0 0x100d0000 0x0 0x20000>;
  355. interrupt-parent = <&plic>;
  356. interrupts = <31>;
  357. clocks = <&hfclk>;
  358. };
  359. /*gmac device configuration*/
  360. stmmac_axi_setup: stmmac-axi-config {
  361. snps,wr_osr_lmt = <0xf>;
  362. snps,rd_osr_lmt = <0xf>;
  363. snps,blen = <256 128 64 32 0 0 0>;
  364. };
  365. gmac:gmac@10020000{
  366. compatible = "snps,dwmac";
  367. reg = <0x0 0x10020000 0x0 0x10000>;
  368. interrupt-parent = <&plic>;
  369. interrupts = <6 7>;
  370. interrupt-names = "macirq","eth_wake_irq";
  371. max-frame-size = <9000>;
  372. phy-mode = "rgmii-txid";
  373. snps,multicast-filter-bins = <256>;
  374. snps,perfect-filter-entries = <128>;
  375. rx-fifo-depth = <32768>;
  376. tx-fifo-depth = <16384>;
  377. clocks = <&gmacclk>;
  378. clock-names = "stmmaceth";
  379. snps,fixed-burst = <1>;
  380. snps,no-pbl-x8 = <1>;
  381. /*snps,force_sf_dma_mode;*/
  382. snps,force_thresh_dma_mode;
  383. snps,axi-config = <&stmmac_axi_setup>;
  384. };
  385. nbdla: nvdla@0x11940000 {
  386. compatible = "nvidia,nvdla_os_initial";
  387. interrupt-parent = <&plic>;
  388. interrupts = <22>;
  389. memory-region = <&nvdla_reserved>;
  390. reg = <0x0 0x11940000 0x0 0x40000>;
  391. status = "okay";
  392. };
  393. jpu:coadj12@11900000 {
  394. compatible = "cm,codaj12-jpu-1";
  395. reg = <0x0 0x11900000 0x0 0x300>;
  396. memory-region = <&jpu_reserved>;
  397. interrupt-parent = <&plic>;
  398. interrupts = <24>;
  399. clocks = <&jpuclk>;
  400. clock-names = "jpege";
  401. reg-names = "control";
  402. status = "okay";
  403. };
  404. vpu_dec:vpu_dec@118F0000 {
  405. compatible = "c&m,cm511-vpu";
  406. reg = <0 0x118F0000 0 0x10000>;
  407. //memory-region = <&vpu_reserved>;
  408. interrupt-parent = <&plic>;
  409. interrupts = <23>;
  410. clocks = <&vpuclk>;
  411. clock-names = "vcodec";
  412. status = "okay";
  413. };
  414. vpu_enc:vpu_enc@118E0000 {
  415. compatible = "cm,cm521-vpu";
  416. reg = <0x0 0x118E0000 0x0 0x4000>;
  417. interrupt-parent = <&plic>;
  418. interrupts = <26>;
  419. clocks = <&vpuclk>;
  420. clock-names = "vcodec";
  421. reg-names = "control";
  422. };
  423. ptc: pwm@12490000 {
  424. compatible = "starfive,pwm0";
  425. reg = <0x0 0x12490000 0x0 0x10000>;
  426. reg-names = "control";
  427. sifive,approx-period = <100000000>;
  428. clocks = <&pwmclk>;
  429. #pwm-cells=<3>;
  430. sifive,npwm = <8>;
  431. };
  432. sfc_tmp:tmpsensor@124A0000 {
  433. compatible = "sfc,tempsensor";
  434. reg = <0x0 0x124A0000 0x0 0x1000>;
  435. interrupt-parent = <&plic>;
  436. interrupts = <122>;
  437. status = "okay";
  438. };
  439. qspi:qspi@11860000 {
  440. compatible = "cadence,qspi","cdns,qspi-nor";
  441. #address-cells = <1>;
  442. #size-cells = <0>;
  443. reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >;
  444. interrupts = <3>;
  445. interrupt-parent = <&plic>;
  446. clocks = <&qspi_clk>;
  447. cdns,fifo-depth = <256>;
  448. cdns,fifo-width = <4>;
  449. cdns,trigger-address = <0x00000000>;
  450. status = "okay";
  451. spi-max-frequency = <250000000>;
  452. nor_flash:nor-flash@0 {
  453. compatible = "spi-flash";
  454. reg=<0>;
  455. spi-max-frequency = <100000000>;
  456. page-size = <256>;
  457. block-size = <16>;
  458. cdns,read-delay = <4>;
  459. cdns,tshsl-ns = <1>;
  460. cdns,tsd2d-ns = <1>;
  461. cdns,tchsh-ns = <1>;
  462. cdns,tslch-ns = <1>;
  463. spi-tx-bus-width = <1>;
  464. spi-rx-bus-width = <1>;
  465. };
  466. };
  467. spi2:spi2@12410000 {
  468. compatible = "snps,dw-apb-ssi";
  469. #address-cells = <1>;
  470. #size-cells = <0>;
  471. interrupt-parent = <&plic>;
  472. interrupts = <70>;
  473. reg = <0x0 0x12410000 0x0 0x10000>;
  474. clocks = <&spiclk>;
  475. /*num-cs = <1>;
  476. cs-gpios = <&gpio 0 0>;*/
  477. spi_dev0: spi@0 {
  478. compatible = "rohm,dh2228fv";
  479. spi-max-frequency = <10000000>;
  480. reg = <0>;
  481. status = "okay";
  482. };
  483. };
  484. xrp@0 {
  485. compatible = "cdns,xrp";
  486. reg = <0x0 0xf0000000 0x0 0x01ffffff
  487. 0x10 0x72000000 0x0 0x00001000
  488. 0x10 0x72001000 0x0 0x00fff000
  489. 0x0 0x124b0000 0x0 0x00010000>;
  490. clocks = <&hfclk>;
  491. interrupt-parent = <&plic>;
  492. firmware-name = "vp6_elf";
  493. dsp-irq = <19 20>;
  494. dsp-irq-src = <0x20 0x21>;
  495. intc-irq-mode = <1>;
  496. intc-irq = <0 1>;
  497. interrupts = <27 28>;
  498. #address-cells = <1>;
  499. #size-cells = <1>;
  500. ranges = <0x40000000 0x0 0x40000000 0x01000000
  501. 0xb0000000 0x10 0x70000000 0x3000000>;
  502. dsp@0 {
  503. };
  504. };
  505. sdio0:sdio0@10000000{
  506. compatible = "snps,dw-mshc";
  507. reg = <0x0 0x10000000 0x0 0x10000>;
  508. interrupts = <4>;
  509. interrupt-parent = <&plic>;
  510. clocks = <&dwmmc_biuclk>;
  511. clock-names = "biu";
  512. clock-frequency = <100000000>;
  513. max-frequency = <50000000>;
  514. fifo-depth = <32>;
  515. card-detect-delay = <300>;
  516. fifo-watermark-aligned;
  517. data-addr = <0>;
  518. bus-width = <4>;
  519. cap-sd-highspeed;
  520. /*broken-cd;*/
  521. cap-sdio-irq;
  522. cap-mmc-hw-reset;
  523. non-removable;
  524. enable-sdio-wakeup;
  525. keep-power-in-suspend;
  526. /*cap-power-off-card;*/
  527. cap-mmc-highspeed;
  528. /*fixed-emmc-driver-type;*/
  529. post-power-on-delay-ms = <200>;
  530. };
  531. sdio1:sdio1@10010000{
  532. compatible = "snps,dw-mshc";
  533. reg = <0x0 0x10010000 0x0 0x10000>;
  534. interrupts = <5>;
  535. interrupt-parent = <&plic>;
  536. clocks = <&dwmmc_biuclk>;
  537. clock-names = "biu";
  538. clock-frequency = <100000000>;
  539. max-frequency = <26000000>;
  540. fifo-depth = <32>;
  541. card-detect-delay = <300>;
  542. fifo-watermark-aligned;
  543. data-addr = <0>;
  544. bus-width = <4>;
  545. cap-sd-highspeed;
  546. /*broken-cd;*/
  547. cap-sdio-irq;
  548. cap-mmc-hw-reset;
  549. non-removable;
  550. enable-sdio-wakeup;
  551. keep-power-in-suspend;
  552. /*cap-power-off-card;*/
  553. cap-mmc-highspeed;
  554. /*fixed-emmc-driver-type;*/
  555. post-power-on-delay-ms = <200>;
  556. };
  557. sfivefb:sfivefb@12000000 {
  558. compatible = "starfive,vpp-lcdc";
  559. interrupt-parent = <&plic>;
  560. interrupts = <101>, <103>;
  561. interrupt-names = "lcdc_irq", "vpp1_irq";
  562. reg = <0x0 0x12000000 0x0 0x10000>,
  563. <0x0 0x12100000 0x0 0x10000>,
  564. <0x0 0x12040000 0x0 0x10000>,
  565. <0x0 0x12080000 0x0 0x10000>,
  566. <0x0 0x120c0000 0x0 0x10000>,
  567. <0x0 0x12240000 0x0 0x10000>,
  568. <0x0 0x12250000 0x0 0x10000>,
  569. <0x0 0x12260000 0x0 0x10000>;
  570. reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
  571. memory-region = <&sffb_reserved>;
  572. clocks = <&uartclk>, <&apb2clk>;
  573. clock-names = "baudclk", "apb_pclk";
  574. status = "okay";
  575. ddr-format = <WIN_FMT_RGB565>;
  576. pp1 {
  577. pp-id = <1>;
  578. fifo-out;
  579. src-format = <COLOR_YUV420_NV21>;
  580. src-width = <1920>;
  581. src-height = <1080>;
  582. dst-format = <COLOR_RGB888_ARGB>;
  583. dst-width = <1920>;
  584. dst-height = <1080>;
  585. };
  586. };
  587. vin_sysctl:vin_sysctl@19800000 {
  588. compatible = "starfive,stf-vin";
  589. reg = <0x0 0x19800000 0x0 0x10000>,
  590. <0x0 0x19810000 0x0 0x10000>,
  591. <0x0 0x19820000 0x0 0x10000>,
  592. <0x0 0x19830000 0x0 0x10000>,
  593. <0x0 0x19840000 0x0 0x10000>,
  594. <0x0 0x19870000 0x0 0x30000>,
  595. <0x0 0x198a0000 0x0 0x30000>,
  596. <0x0 0x11800000 0x0 0x10000>,
  597. <0x0 0x11840000 0x0 0x10000>,
  598. <0x0 0x11858000 0x0 0x10000>;
  599. reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad";
  600. interrupt-parent = <&plic>;
  601. interrupts = <119 109>;
  602. memory-region = <&vin_reserved>;
  603. /*for imx219 vim&isp*/
  604. format = <SRC_CSI2RX_VIN_ISP>;
  605. frame-width = <1920>;
  606. frame-height =<1080>;
  607. /*defaule config sc2235
  608. format = <SRC_DVP_SENSOR_VIN_ISP>;
  609. frame-width = <1920>;
  610. frame-height =<1080>;
  611. isp0_enable;*/
  612. /*defaule config ov5640
  613. format = <SRC_DVP_SENSOR_VIN_OV5640>;
  614. frame-width = <1920>;
  615. frame-height =<1080>;*/
  616. /*defaule config for ov4689 vin&isp
  617. format = <SRC_CSI2RX_VIN_ISP>;
  618. frame-width = <800>;
  619. frame-height =<480>;
  620. */
  621. isp0_enable;
  622. csi-lane = <2>;
  623. csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
  624. csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
  625. csi-clane-swap = /bits/ 8 <0>;
  626. csi-clane-pn-swap = /bits/ 8 <0>;
  627. csi-mipiID = <0>;
  628. csi-width = <1920>;
  629. csi-height = <1080>;
  630. csi-dt = <0x2b>;
  631. };
  632. i2sadc0: i2sadc0@10400000 {
  633. compatible = "snps,designware-i2sadc0";
  634. reg = <0x0 0x10400000 0x0 0x1000>;
  635. interrupt-parent = <&plic>;
  636. /*interrupts = <59>;*/
  637. /*interrupt-names = "rx";*/
  638. clocks = <&apb1clk>;
  639. clock-names = "i2sclk";
  640. #sound-dai-cells = <0>;
  641. dmas = <&dma2p 28>;
  642. dma-names = "rx";
  643. };
  644. i2svad: i2svad@10420000 {
  645. compatible = "sf,sf-i2svad";
  646. reg = <0x0 0x10420000 0x0 0x1000> ;
  647. interrupt-parent = <&plic>;
  648. interrupts = <60>, <61>;
  649. interrupt-names = "spintr", "slintr";
  650. clocks = <&apb1clk>;
  651. clock-names = "i2sclk";
  652. #sound-dai-cells = <0>;
  653. };
  654. i2sdac0: i2sdac0@10450000 {
  655. compatible = "snps,designware-i2sdac0";
  656. reg = <0x0 0x10450000 0x0 0x1000>;
  657. interrupt-parent = <&plic>;
  658. /*interrupts = <64>; */
  659. /*interrupt-names = "tx";*/
  660. clocks = <&apb1clk>;
  661. clock-names = "i2sclk";
  662. #sound-dai-cells = <0>;
  663. dmas = <&dma2p 30>;
  664. dma-names = "tx";
  665. };
  666. i2sdac1: i2sdac1@10460000 {
  667. compatible = "snps,designware-i2sdac1";
  668. reg = <0x0 0x10460000 0x0 0x1000>;
  669. interrupt-parent = <&plic>;
  670. /*interrupts = <66>;*/
  671. /*interrupt-names = "tx";*/
  672. clocks = <&apb1clk>;
  673. clock-names = "i2sclk";
  674. #sound-dai-cells = <0>;
  675. dmas = <&dma2p 31>;
  676. dma-names = "tx";
  677. };
  678. i2sdac16k: i2sdac16k@10470000 {
  679. compatible = "snps,designware-i2sdac16k";
  680. reg = <0x0 0x10470000 0x0 0x1000>;
  681. interrupt-parent = <&plic>;
  682. /* interrupts = <68>; */
  683. /* interrupt-names = "tx"; */
  684. clocks = <&apb1clk>;
  685. clock-names = "i2sclk";
  686. #sound-dai-cells = <0>;
  687. dmas = <&dma2p 29>;
  688. dma-names = "tx";
  689. };
  690. spdif0: spdif0@10430000 {
  691. compatible = "starfive,sf-spdif";
  692. reg = <0x0 0x10430000 0x0 0x1000>;
  693. interrupt-parent = <&plic>;
  694. interrupts = <62>;
  695. interrupt-names = "tx";
  696. clocks = <&audioclk>;
  697. clock-names = "audioclk";
  698. #sound-dai-cells = <0>;
  699. };
  700. pdm: pdm@10410000 {
  701. compatible = "starfive,sf-pdm";
  702. reg = <0x0 0x10410000 0x0 0x1000>, <0x0 0x10480000 0x0 0x1000>;
  703. reg-names = "pdm", "audio-clk";
  704. clocks = <&audioclk>;
  705. clock-names = "audioclk";
  706. #sound-dai-cells = <0>;
  707. };
  708. ac108_mclk: ac108_mclk {
  709. compatible = "fixed-clock";
  710. #clock-cells = <0>;
  711. clock-frequency = <24576000>;
  712. };
  713. wm8960_mclk: wm8960_mclk {
  714. compatible = "fixed-clock";
  715. #clock-cells = <0>;
  716. clock-frequency = <24576000>;
  717. };
  718. spdif_transmitter: spdif_transmitter {
  719. compatible = "linux,spdif-dit";
  720. #sound-dai-cells = <0>;
  721. };
  722. spdif_receiver: spdif_receiver {
  723. compatible = "linux,spdif-dir";
  724. #sound-dai-cells = <0>;
  725. };
  726. pwmdac: pwmdac@10440000 {
  727. compatible = "sf,pwmdac";
  728. reg = <0x0 0x10440000 0x0 0x1000>;
  729. clocks = <&apb1clk>;
  730. dmas = <&dma2p 23>;
  731. dma-names = "tx";
  732. #sound-dai-cells = <0>;
  733. };
  734. pwmdac_codec: pwmdac-transmitter {
  735. compatible = "linux,pwmdac-dit";
  736. #sound-dai-cells = <0>;
  737. };
  738. dmic_codec: dmic_codec {
  739. compatible = "dmic-codec";
  740. #sound-dai-cells = <0>;
  741. };
  742. sound:snd-card{
  743. compatible = "simple-audio-card";
  744. simple-audio-card,name = "Starfive-Multi-Sound-Card";
  745. /* pwmdac */
  746. simple-audio-card,dai-link@0 {
  747. reg = <0>;
  748. status = "okay";
  749. format = "left_j";
  750. bitclock-master = <&sndcpu0>;
  751. frame-master = <&sndcpu0>;
  752. sndcpu0: cpu {
  753. sound-dai = <&pwmdac>;
  754. };
  755. codec {
  756. sound-dai = <&pwmdac_codec>;
  757. };
  758. };
  759. };
  760. };
  761. };
  762. #include "tda998x_1080p.dtsi"
  763. /* #include "codecs/sf_pdm.dtsi" */
  764. /* #include "codecs/sf_spdif.dtsi" */
  765. /* #include "codecs/sf_ac108.dtsi" */
  766. /* #include "codecs/sf_wm8960.dtsi" */
  767. /* #include "codecs/sf_vad.dtsi" */