starfive_vic7100_evb.dts 12 KB

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  1. /dts-v1/;
  2. #include "starfive_vic7100_clk.dtsi"
  3. / {
  4. #address-cells = <2>;
  5. #size-cells = <2>;
  6. compatible = "sifive,freedom-u74-arty";
  7. model = "sifive,freedom-u74-arty";
  8. chosen {
  9. linux,initrd-start = <0x0 0x86100000>;
  10. linux,initrd-end = <0x0 0x8c000000>;
  11. stdout-path = "/soc/serial@12440000:115200";
  12. #bootargs = "debug console=ttyS0 rootwait";
  13. };
  14. aliases {
  15. spi0="/soc/qspi@11860000";
  16. mshc0="/soc/sdio0@10000000";
  17. };
  18. cpus: cpus {
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. timebase-frequency = <6250000>;
  22. compatible = "starfive,fu74-g000";
  23. cpu@0 {
  24. clock-frequency = <0>;
  25. compatible = "starfive,rocket0", "riscv";
  26. d-cache-block-size = <64>;
  27. d-cache-sets = <64>;
  28. d-cache-size = <32768>;
  29. d-tlb-sets = <1>;
  30. d-tlb-size = <32>;
  31. device_type = "cpu";
  32. i-cache-block-size = <64>;
  33. i-cache-sets = <64>;
  34. i-cache-size = <32768>;
  35. i-tlb-sets = <1>;
  36. i-tlb-size = <32>;
  37. mmu-type = "riscv,sv39";
  38. next-level-cache = <&cachectrl>;
  39. reg = <0>;
  40. riscv,isa = "rv64imafdc";
  41. starfive,itim = <&itim0>;
  42. status = "okay";
  43. tlb-split;
  44. cpu0intctrl: interrupt-controller {
  45. #interrupt-cells = <1>;
  46. compatible = "riscv,cpu-intc";
  47. interrupt-controller;
  48. };
  49. };
  50. cpu@1 {
  51. clock-frequency = <0>;
  52. compatible = "starfive,rocket0", "riscv";
  53. d-cache-block-size = <64>;
  54. d-cache-sets = <64>;
  55. d-cache-size = <32768>;
  56. d-tlb-sets = <1>;
  57. d-tlb-size = <32>;
  58. device_type = "cpu";
  59. i-cache-block-size = <64>;
  60. i-cache-sets = <64>;
  61. i-cache-size = <32768>;
  62. i-tlb-sets = <1>;
  63. i-tlb-size = <32>;
  64. mmu-type = "riscv,sv39";
  65. next-level-cache = <&cachectrl>;
  66. reg = <1>;
  67. riscv,isa = "rv64imafdc";
  68. starfive,itim = <&itim1>;
  69. status = "okay";
  70. tlb-split;
  71. cpu1intctrl: interrupt-controller {
  72. #interrupt-cells = <1>;
  73. compatible = "riscv,cpu-intc";
  74. interrupt-controller;
  75. };
  76. };
  77. };
  78. memory@80000000 {
  79. device_type = "memory";
  80. reg = <0x0 0x80000000 0x2 0x0>;
  81. };
  82. memory@3000000000 {
  83. device_type = "memory";
  84. reg = <0x30 0x0 0x0 0x0>;
  85. };
  86. reserved-memory {
  87. #address-cells = <2>;
  88. #size-cells = <2>;
  89. ranges;
  90. linux,cma {
  91. compatible = "shared-dma-pool";
  92. reusable;
  93. size = <0x0 0x28000000>;
  94. alignment = <0x0 0x1000>;
  95. alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
  96. linux,cma-default;
  97. };
  98. jpu_reserved: framebuffer@c9000000 {
  99. reg = <0x0 0xc9000000 0x0 0x2000000>;
  100. };
  101. nvdla_reserved:framebuffer@d0000000{
  102. reg = <0x0 0xd0000000 0x0 0x28000000>;
  103. };
  104. };
  105. soc {
  106. #address-cells = <2>;
  107. #size-cells = <2>;
  108. #clock-cells = <1>;
  109. compatible = "starfive,freedom-u74-arty", "simple-bus";
  110. ranges;
  111. cachectrl: cache-controller@2010000 {
  112. cache-block-size = <64>;
  113. cache-level = <2>;
  114. cache-sets = <2048>;
  115. cache-size = <2097152>;
  116. cache-unified;
  117. compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
  118. interrupt-parent = <&plic>;
  119. interrupts = <1 2 3>;
  120. /*next-level-cache = <&L40 &L36>;*/
  121. reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
  122. reg-names = "control", "sideband";
  123. };
  124. dtim: dtim@1000000 {
  125. compatible = "starfive,dtim0";
  126. reg = <0x0 0x1000000 0x0 0x2000>;
  127. reg-names = "mem";
  128. };
  129. itim0: itim@1808000 {
  130. compatible = "starfive,itim0";
  131. reg = <0x0 0x1808000 0x0 0x8000>;
  132. reg-names = "mem";
  133. };
  134. itim1: itim@1820000 {
  135. compatible = "starfive,itim0";
  136. reg = <0x0 0x1820000 0x0 0x8000>;
  137. reg-names = "mem";
  138. };
  139. clint: clint@2000000 {
  140. #interrupt-cells = <1>;
  141. compatible = "riscv,clint0";
  142. interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;
  143. reg = <0x0 0x2000000 0x0 0x10000>;
  144. reg-names = "control";
  145. };
  146. plic: plic@c000000 {
  147. #interrupt-cells = <1>;
  148. compatible = "riscv,plic0";
  149. interrupt-controller;
  150. interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;
  151. reg = <0x0 0xc000000 0x0 0x4000000>;
  152. reg-names = "control";
  153. riscv,max-priority = <7>;
  154. riscv,ndev = <127>;
  155. };
  156. uart3: serial@12440000 {
  157. compatible = "snps,dw-apb-uart";
  158. interrupt-parent = <&plic>;
  159. interrupts = <73>;
  160. reg = <0x0 0x12440000 0x0 0x10000>;
  161. reg-io-width = <4>;
  162. reg-shift = <2>;
  163. clocks = <&uartclk>, <&apb2clk>;
  164. clock-names = "baudclk", "apb_pclk";
  165. current-clock = <100000000>;
  166. current-speed = <115200>;
  167. status = "okay";
  168. };
  169. uart2: serial@12430000 {
  170. compatible = "snps,dw-apb-uart";
  171. interrupt-parent = <&plic>;
  172. interrupts = <72>;
  173. reg = <0x0 0x12430000 0x0 0x10000>;
  174. reg-io-width = <4>;
  175. reg-shift = <2>;
  176. clocks = <&uartclk>, <&apb2clk>;
  177. clock-names = "baudclk", "apb_pclk";
  178. current-clock = <100000000>;
  179. current-speed = <115200>;
  180. status = "disabled";
  181. };
  182. uart1: hs_serial@11880000 {
  183. compatible = "snps,dw-apb-uart";
  184. interrupt-parent = <&plic>;
  185. interrupts = <93>;
  186. reg = <0x0 0x11880000 0x0 0x10000>;
  187. reg-io-width = <4>;
  188. reg-shift = <2>;
  189. clocks = <&hs_uartclk>, <&apb1clk>;
  190. clock-names = "baudclk","apb_pclk";
  191. current-clock = <74250000>;
  192. current-speed = <115200>;
  193. status = "okay";
  194. };
  195. uart0: hs_serial@11870000 {
  196. compatible = "snps,dw-apb-uart";
  197. interrupt-parent = <&plic>;
  198. interrupts = <92>;
  199. reg = <0x0 0x11870000 0x0 0x10000>;
  200. reg-io-width = <4>;
  201. reg-shift = <2>;
  202. clocks = <&hs_uartclk>, <&apb1clk>;
  203. clock-names = "baudclk", "apb_pclk";
  204. current-clock = <74250000>;
  205. current-speed = <115200>;
  206. status = "okay";
  207. };
  208. dma2p: sgdma2p@100b0000 {
  209. compatible = "snps,axi-dma-1.01a";
  210. reg = <0x0 0x100b0000 0x0 0x10000>;
  211. clocks = <&axiclk>,<&ahb0clk>;
  212. clock-names = "core-clk", "cfgr-clk";
  213. interrupt-parent = <&plic>;
  214. interrupts = <2>;
  215. dma-channels = <4>;
  216. snps,dma-masters = <1>;
  217. snps,data-width = <4>;
  218. snps,block-size = <4096 4096 4096 4096>;
  219. snps,priority = <0 1 2 3>;
  220. snps,axi-max-burst-len = <128>;
  221. status = "okay";
  222. };
  223. dma1p: sgdma1p@10500000 {
  224. compatible = "snps,axi-dma-1.01a";
  225. reg = <0x0 0x10500000 0x0 0x10000>;
  226. clocks = <&axiclk>,<&ahb0clk>;
  227. clock-names = "core-clk", "cfgr-clk";
  228. interrupt-parent = <&plic>;
  229. interrupts = <1>;
  230. dma-channels = <16>;
  231. snps,dma-masters = <1>;
  232. snps,data-width = <3>;
  233. snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
  234. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  235. snps,axi-max-burst-len = <64>;
  236. status = "okay";
  237. };
  238. usb3_phy: usb3-phy {
  239. compatible = "usb3-phy";
  240. status = "okay";
  241. };
  242. usb2_phy: usb2-phy {
  243. compatible = "usb2-phy";
  244. status = "okay";
  245. };
  246. USB30: usb@104c0000 {
  247. compatible = "cdns,usb3";
  248. reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
  249. <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
  250. <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
  251. reg-names = "otg", "xhci", "dev";
  252. interrupt-parent = <&plic>;
  253. interrupts = <43>, <44>, <52>;
  254. interrupt-names = "otg",
  255. "host",
  256. "peripheral";
  257. phys = <&usb3_phy>, <&usb2_phy>;
  258. phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
  259. status = "okay";
  260. /*maximum-speed = "high-speed";
  261. dr_mode = "host";*/
  262. };
  263. gpio: gpio@11910000 {
  264. compatible = "starfive,gpio0";
  265. interrupt-parent = <&plic>;
  266. interrupts = <32>;
  267. reg = <0x0 0x11910000 0x0 0x10000>;
  268. reg-names = "control";
  269. interrupt-controller;
  270. #gpio-cells = <2>;
  271. };
  272. gpiorst:gpio-restart {
  273. compatible = "gpio-restart";
  274. gpios = <&gpio 10 1>;
  275. };
  276. i2c0: i2c@118b0000 {
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. compatible = "snps,designware-i2c";
  280. reg = <0x0 0x118b0000 0x0 0x10000>;
  281. interrupt-parent = <&plic>;
  282. interrupts = <96>;
  283. /*clocks = <&hfclk>; */
  284. clock-frequency = <1000000>;
  285. i2c-sda-hold-time-ns = <300>;
  286. i2c-sda-falling-time-ns = <5000>;
  287. i2c-scl-falling-time-ns = <5000>;
  288. };
  289. trng: trng@118d0000 {
  290. compatible = "starfive,vic-rng";
  291. reg = <0x0 0x118d0000 0x0 0x10000>;
  292. interrupt-parent = <&plic>;
  293. interrupts = <98>;
  294. clocks = <&hfclk>;
  295. };
  296. crypto: crypto@100d0000 {
  297. compatible = "starfive,vic-sec";
  298. reg = <0x0 0x100d0000 0x0 0x20000>;
  299. interrupt-parent = <&plic>;
  300. interrupts = <31>;
  301. clocks = <&hfclk>;
  302. };
  303. /*gmac device configuration*/
  304. stmmac_axi_setup: stmmac-axi-config {
  305. snps,wr_osr_lmt = <0xf>;
  306. snps,rd_osr_lmt = <0xf>;
  307. snps,blen = <256 128 64 32 0 0 0>;
  308. };
  309. gmac:gmac@10020000{
  310. compatible = "snps,dwmac";
  311. reg = <0x0 0x10020000 0x0 0x10000>;
  312. interrupt-parent = <&plic>;
  313. interrupts = <6 7>;
  314. interrupt-names = "macirq","eth_wake_irq";
  315. max-frame-size = <9000>;
  316. phy-mode = "rgmii-txid";
  317. snps,multicast-filter-bins = <256>;
  318. snps,perfect-filter-entries = <128>;
  319. rx-fifo-depth = <32768>;
  320. tx-fifo-depth = <16384>;
  321. clocks = <&gmacclk>;
  322. clock-names = "stmmaceth";
  323. snps,fixed-burst = <1>;
  324. snps,no-pbl-x8 = <1>;
  325. /*snps,force_sf_dma_mode;*/
  326. snps,force_thresh_dma_mode;
  327. snps,axi-config = <&stmmac_axi_setup>;
  328. };
  329. nbdla: nvdla@0x11940000 {
  330. compatible = "nvidia,nvdla_os_initial";
  331. interrupt-parent = <&plic>;
  332. interrupts = <22>;
  333. memory-region = <&nvdla_reserved>;
  334. reg = <0x0 0x11940000 0x0 0x40000>;
  335. status = "okay";
  336. };
  337. jpu:coadj12@11900000 {
  338. compatible = "cm,codaj12-jpu-1";
  339. reg = <0x0 0x11900000 0x0 0x300>;
  340. memory-region = <&jpu_reserved>;
  341. interrupt-parent = <&plic>;
  342. interrupts = <24>;
  343. clocks = <&jpuclk>;
  344. clock-names = "jpege";
  345. reg-names = "control";
  346. status = "okay";
  347. };
  348. vpu_dec:vpu_dec@118F0000 {
  349. compatible = "c&m,cm511-vpu";
  350. reg = <0 0x118F0000 0 0x10000>;
  351. //memory-region = <&vpu_reserved>;
  352. interrupt-parent = <&plic>;
  353. interrupts = <23>;
  354. clocks = <&vpuclk>;
  355. clock-names = "vcodec";
  356. status = "okay";
  357. };
  358. vpu_enc:vpu_enc@118E0000 {
  359. compatible = "cm,cm521-vpu";
  360. reg = <0x0 0x118E0000 0x0 0x4000>;
  361. interrupt-parent = <&plic>;
  362. interrupts = <26>;
  363. clocks = <&vpuclk>;
  364. clock-names = "vcodec";
  365. reg-names = "control";
  366. };
  367. ptc: pwm@12490000 {
  368. compatible = "sifive,pwm0";
  369. reg = <0x0 0x12490000 0x0 0x10000>;
  370. reg-names = "control";
  371. sifive,approx-period = <100000000>;
  372. #pwm-cells=<3>;
  373. sifive,npwm = <8>;
  374. };
  375. qspi:qspi@11860000 {
  376. compatible = "cadence,qspi","cdns,qspi-nor";
  377. #address-cells = <1>;
  378. #size-cells = <0>;
  379. reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >;
  380. interrupts = <3>;
  381. interrupt-parent = <&plic>;
  382. clocks = <&qspi_clk>;
  383. cdns,fifo-depth = <256>;
  384. cdns,fifo-width = <4>;
  385. cdns,trigger-address = <0x00000000>;
  386. status = "okay";
  387. spi-max-frequency = <250000000>;
  388. nor_flash:nor-flash@0 {
  389. compatible = "spi-flash";
  390. reg=<0>;
  391. spi-max-frequency = <100000000>;
  392. page-size = <256>;
  393. block-size = <16>;
  394. cdns,read-delay = <4>;
  395. cdns,tshsl-ns = <1>;
  396. cdns,tsd2d-ns = <1>;
  397. cdns,tchsh-ns = <1>;
  398. cdns,tslch-ns = <1>;
  399. spi-tx-bus-width = <1>;
  400. spi-rx-bus-width = <1>;
  401. };
  402. };
  403. xrp@0 {
  404. compatible = "cdns,xrp";
  405. reg = <0x0 0xf0000000 0x0 0x01ffffff
  406. 0x10 0x72000000 0x0 0x00001000
  407. 0x10 0x72001000 0x0 0x00fff000
  408. 0x0 0x124b0000 0x0 0x00010000>;
  409. clocks = <&hfclk>;
  410. interrupt-parent = <&plic>;
  411. firmware-name = "vp6_elf";
  412. dsp-irq = <19 20>;
  413. dsp-irq-src = <0x20 0x21>;
  414. intc-irq-mode = <1>;
  415. intc-irq = <0 1>;
  416. interrupts = <27 28>;
  417. #address-cells = <1>;
  418. #size-cells = <1>;
  419. ranges = <0x40000000 0x0 0x40000000 0x01000000
  420. 0xb0000000 0x10 0x70000000 0x3000000>;
  421. dsp@0 {
  422. };
  423. };
  424. sdio0:sdio0@10000000{
  425. compatible = "snps,dw-mshc";
  426. reg = <0x0 0x10000000 0x0 0x10000>;
  427. interrupts = <4>;
  428. interrupt-parent = <&plic>;
  429. clocks = <&dwmmc_biuclk>;
  430. clock-names = "biu";
  431. clock-frequency = <100000000>;
  432. max-frequency = <26000000>;
  433. fifo-depth = <32>;
  434. card-detect-delay = <300>;
  435. fifo-watermark-aligned;
  436. data-addr = <0>;
  437. bus-width = <4>;
  438. cap-sd-highspeed;
  439. /*broken-cd;*/
  440. cap-sdio-irq;
  441. cap-mmc-hw-reset;
  442. non-removable;
  443. enable-sdio-wakeup;
  444. keep-power-in-suspend;
  445. /*cap-power-off-card;*/
  446. cap-mmc-highspeed;
  447. /*fixed-emmc-driver-type;*/
  448. post-power-on-delay-ms = <200>;
  449. };
  450. };
  451. };