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Merge branch 'starfive' of https://github.com/starfive-tech/sft-riscv-uboot into starfive

david.li 3 年之前
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1cb30d5dcf
共有 3 个文件被更改,包括 56 次插入0 次删除
  1. 5 0
      arch/riscv/dts/starfive_vic7100_clk.dtsi
  2. 17 0
      arch/riscv/dts/starfive_vic7100_evb.dts
  3. 34 0
      board/starfive/vic7100/vic7100.c

+ 5 - 0
arch/riscv/dts/starfive_vic7100_clk.dtsi

@@ -85,4 +85,9 @@
             compatible = "fixed-clock";
             clock-frequency = <125000000>;
        };
+	spiclk: spiclk {
+	    #clock-cells = <0>;
+            compatible = "fixed-clock";
+            clock-frequency = <50000000>;
+	};
 };

+ 17 - 0
arch/riscv/dts/starfive_vic7100_evb.dts

@@ -481,6 +481,23 @@
 				spi-rx-bus-width = <1>;
 			};
 		};
+		spi2:spi2@12410000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupt-parent = <&plic>;
+			interrupts = <70>;
+			reg = <0x0 0x12410000 0x0 0x10000>;
+			clocks = <&spiclk>;
+			/*num-cs = <1>;
+			cs-gpios = <&gpio 0 0>;*/
+			spi_dev0: spi@0 {
+				compatible = "rohm,dh2228fv";
+				spi-max-frequency = <10000000>;
+				reg = <0>;
+				status = "okay";
+			};
+		};
 		xrp@0 {
 		compatible = "cdns,xrp";
 		reg = <0x0 0xf0000000 0x0 0x01ffffff

+ 34 - 0
board/starfive/vic7100/vic7100.c

@@ -69,6 +69,21 @@ struct sifive_gpio_regs
 	volatile uint32_t  OUT_XOR;     /* 0x0040 */
 };
 
+#define SET_SPI_GPIO_TEST
+
+#ifdef SET_SPI_GPIO_TEST
+#define SET_SPI_GPIO(id,sdo,sdi,sclk,cs) {         \
+	        SET_GPIO_##sdo##_dout_spi##id##_pad_txd;		\
+	        SET_GPIO_##sdo##_doen_LOW;							\
+	        SET_GPIO_spi##id##_pad_rxd(sdi);				\
+	        SET_GPIO_##sdi##_doen_HIGH;							\
+	        SET_GPIO_##sclk##_dout_spi##id##_pad_sck_out;	\
+	        SET_GPIO_##sclk##_doen_LOW;							\
+	        SET_GPIO_##cs##_dout_spi##id##_pad_ss_0_n;		\
+	        SET_GPIO_##cs##_doen_LOW;							\
+	        }
+#endif
+
 #define INIT_FUNC_DEF(name)			\
 	static void _##name##_init(void)
 
@@ -668,6 +683,11 @@ INIT_FUNC_DEF(spi2)
 
 	_CLEAR_RESET_rstgen_rstn_spi2_apb_;
 	_CLEAR_RESET_rstgen_rstn_spi2_core_;
+
+#ifdef SET_SPI_GPIO_TEST
+	/* Modifying the GPIO interface of SPI2 */
+	SET_SPI_GPIO(2,18,16,12,15);
+#endif
 }
 
 INIT_FUNC_DEF(spi3)
@@ -748,6 +768,19 @@ INIT_FUNC_DEF(ptc)
 	ptc_reset();
 }
 
+INIT_FUNC_DEF(tmp_sensor)
+{
+	_DISABLE_CLOCK_clk_temp_apb_;
+	_ASSERT_RESET_rstgen_rstn_temp_apb_;
+	_DISABLE_CLOCK_clk_temp_sense_;
+	_ASSERT_RESET_rstgen_rstn_temp_sense_;
+
+	_ENABLE_CLOCK_clk_temp_apb_;
+	_CLEAR_RESET_rstgen_rstn_temp_apb_;
+	_ENABLE_CLOCK_clk_temp_sense_;
+	_CLEAR_RESET_rstgen_rstn_temp_sense_;
+}
+
 INIT_FUNC_DEF(vout_subsys)
 {
 	_ENABLE_CLOCK_clk_vout_src_ ;
@@ -890,6 +923,7 @@ int board_hw_init(void)
 	INIT_FUNC_CALL(i2c3);
 	//INIT_FUNC_CALL(wdt);
 	INIT_FUNC_CALL(ptc);
+	INIT_FUNC_CALL(tmp_sensor);
 
 	/** Video Output Subsystem **/
 	INIT_FUNC_CALL(vout_subsys);