platform.c 3.4 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Damien Le Moal <damien.lemoal@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_encoding.h>
  11. #include <sbi/sbi_console.h>
  12. #include <sbi/sbi_const.h>
  13. #include <sbi/sbi_platform.h>
  14. #include <sbi_utils/fdt/fdt_fixup.h>
  15. #include <sbi_utils/irqchip/plic.h>
  16. #include <sbi_utils/serial/sifive-uart.h>
  17. #include <sbi_utils/sys/clint.h>
  18. #include "platform.h"
  19. extern const char dt_k210_start[];
  20. unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
  21. unsigned long arg2, unsigned long arg3,
  22. unsigned long arg4)
  23. {
  24. return (unsigned long)&dt_k210_start[0];
  25. }
  26. static struct plic_data plic = {
  27. .addr = K210_PLIC_BASE_ADDR,
  28. .num_src = K210_PLIC_NUM_SOURCES,
  29. };
  30. static struct clint_data clint = {
  31. .addr = K210_CLINT_BASE_ADDR,
  32. .first_hartid = 0,
  33. .hart_count = K210_HART_COUNT,
  34. .has_64bit_mmio = TRUE,
  35. };
  36. static u32 k210_get_clk_freq(void)
  37. {
  38. u32 clksel0, pll0;
  39. u64 pll0_freq, clkr0, clkf0, clkod0, div;
  40. /*
  41. * If the clock selector is not set, use the base frequency.
  42. * Otherwise, use PLL0 frequency with a frequency divisor.
  43. */
  44. clksel0 = k210_read_sysreg(K210_CLKSEL0);
  45. if (!(clksel0 & 0x1))
  46. return K210_CLK0_FREQ;
  47. /*
  48. * Get PLL0 frequency:
  49. * freq = base frequency * clkf0 / (clkr0 * clkod0)
  50. */
  51. pll0 = k210_read_sysreg(K210_PLL0);
  52. clkr0 = 1 + (pll0 & 0x0000000f);
  53. clkf0 = 1 + ((pll0 & 0x000003f0) >> 4);
  54. clkod0 = 1 + ((pll0 & 0x00003c00) >> 10);
  55. pll0_freq = clkf0 * K210_CLK0_FREQ / (clkr0 * clkod0);
  56. /* Get the frequency divisor from the clock selector */
  57. div = 2ULL << ((clksel0 & 0x00000006) >> 1);
  58. return pll0_freq / div;
  59. }
  60. static int k210_final_init(bool cold_boot)
  61. {
  62. void *fdt;
  63. if (!cold_boot)
  64. return 0;
  65. fdt = sbi_scratch_thishart_arg1_ptr();
  66. fdt_cpu_fixup(fdt);
  67. fdt_fixups(fdt);
  68. return 0;
  69. }
  70. static int k210_console_init(void)
  71. {
  72. return sifive_uart_init(K210_UART_BASE_ADDR, k210_get_clk_freq(),
  73. K210_UART_BAUDRATE);
  74. }
  75. static int k210_irqchip_init(bool cold_boot)
  76. {
  77. int rc;
  78. u32 hartid = current_hartid();
  79. if (cold_boot) {
  80. rc = plic_cold_irqchip_init(&plic);
  81. if (rc)
  82. return rc;
  83. }
  84. return plic_warm_irqchip_init(&plic, hartid * 2, hartid * 2 + 1);
  85. }
  86. static int k210_ipi_init(bool cold_boot)
  87. {
  88. int rc;
  89. if (cold_boot) {
  90. rc = clint_cold_ipi_init(&clint);
  91. if (rc)
  92. return rc;
  93. }
  94. return clint_warm_ipi_init();
  95. }
  96. static int k210_timer_init(bool cold_boot)
  97. {
  98. int rc;
  99. if (cold_boot) {
  100. rc = clint_cold_timer_init(&clint, NULL);
  101. if (rc)
  102. return rc;
  103. }
  104. return clint_warm_timer_init();
  105. }
  106. const struct sbi_platform_operations platform_ops = {
  107. .final_init = k210_final_init,
  108. .console_init = k210_console_init,
  109. .console_putc = sifive_uart_putc,
  110. .console_getc = sifive_uart_getc,
  111. .irqchip_init = k210_irqchip_init,
  112. .ipi_init = k210_ipi_init,
  113. .ipi_send = clint_ipi_send,
  114. .ipi_clear = clint_ipi_clear,
  115. .timer_init = k210_timer_init,
  116. .timer_value = clint_timer_value,
  117. .timer_event_stop = clint_timer_event_stop,
  118. .timer_event_start = clint_timer_event_start,
  119. };
  120. const struct sbi_platform platform = {
  121. .opensbi_version = OPENSBI_VERSION,
  122. .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
  123. .name = "Kendryte K210",
  124. .features = SBI_PLATFORM_HAS_TIMER_VALUE,
  125. .hart_count = K210_HART_COUNT,
  126. .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
  127. .platform_ops_addr = (unsigned long)&platform_ops
  128. };