k210.dts 1.5 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Damien Le Moal <damien.lemoal@wdc.com>
  8. */
  9. /dts-v1/;
  10. / {
  11. #address-cells = <2>;
  12. #size-cells = <2>;
  13. compatible = "kendryte,k210";
  14. chosen {
  15. bootargs = "console=hvc0 earlycon=sbi";
  16. };
  17. cpus {
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. cpu0: cpu@0 {
  21. device_type = "cpu";
  22. clock-frequency = <390000000>;
  23. i-cache-size = <32768>;
  24. d-cache-size = <32768>;
  25. mmu-type = "none";
  26. reg = <0>;
  27. riscv,isa = "rv64imafdc";
  28. status = "okay";
  29. cpu0_intc: interrupt-controller {
  30. #interrupt-cells = <1>;
  31. compatible = "riscv,cpu-intc";
  32. interrupt-controller;
  33. };
  34. };
  35. cpu1: cpu@1 {
  36. device_type = "cpu";
  37. clock-frequency = <390000000>;
  38. d-cache-size = <32768>;
  39. i-cache-size = <32768>;
  40. mmu-type = "none";
  41. reg = <1>;
  42. riscv,isa = "rv64imafdc";
  43. status = "okay";
  44. cpu1_intc: interrupt-controller {
  45. #interrupt-cells = <1>;
  46. compatible = "riscv,cpu-intc";
  47. interrupt-controller;
  48. };
  49. };
  50. };
  51. memory@80000000 {
  52. /* Bank 0: 4 MB, Bank 1: 2 MB, AI chip SRAM: 2MB */
  53. device_type = "memory";
  54. reg = <0x00000000 0x80000000 0x00000000 0x00800000>;
  55. };
  56. plic0: interrupt-controller@C000000 {
  57. #interrupt-cells = <1>;
  58. compatible = "riscv,plic0";
  59. interrupt-controller;
  60. interrupts-extended =
  61. <&cpu0_intc 11 &cpu0_intc 9
  62. &cpu1_intc 11 &cpu1_intc 9>;
  63. reg = <0x0 0xc000000 0x0 0x4000000>;
  64. };
  65. };