platform.h 4.6 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Andes Technology Corporation
  5. *
  6. * Authors:
  7. * Zong Li <zong@andestech.com>
  8. * Nylon Chen <nylon7@andestech.com>
  9. */
  10. #ifndef _AE350_PLATFORM_H_
  11. #define _AE350_PLATFORM_H_
  12. #define AE350_HART_COUNT 4
  13. #define AE350_PLIC_ADDR 0xe4000000
  14. #define AE350_PLIC_NUM_SOURCES 71
  15. #define AE350_PLICSW_ADDR 0xe6400000
  16. #define AE350_PLMT_ADDR 0xe6000000
  17. #define AE350_L2C_ADDR 0xe0500000
  18. #define AE350_UART_ADDR_OFFSET 0x20
  19. #define AE350_UART_ADDR (0xf0300000 + AE350_UART_ADDR_OFFSET)
  20. #define AE350_UART_FREQUENCY 19660800
  21. #define AE350_UART_BAUDRATE 38400
  22. #define AE350_UART_REG_SHIFT 2
  23. #define AE350_UART_REG_WIDTH 0
  24. /*Memory and Miscellaneous Registers*/
  25. #define CSR_MILMB 0x7c0
  26. #define CSR_MDLMB 0x7c1
  27. #define CSR_MECC_CDOE 0x7c2
  28. #define CSR_MNVEC 0x7c3
  29. #define CSR_MPFTCTL 0x7c5
  30. #define CSR_MCACHECTL 0x7ca
  31. #define CSR_MCCTLBEGINADDR 0x7cb
  32. #define CSR_MCCTLCOMMAND 0x7cc
  33. #define CSR_MCCTLDATA 0x7cc
  34. #define CSR_SCCTLDATA 0x9cd
  35. #define CSR_UCCTLBEGINADDR 0x80c
  36. #define CSR_MMISCCTL 0x7d0
  37. enum sbi_ext_andes_fid {
  38. SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
  39. SBI_EXT_ANDES_GET_MMISC_CTL_STATUS,
  40. SBI_EXT_ANDES_SET_MCACHE_CTL,
  41. SBI_EXT_ANDES_SET_MMISC_CTL,
  42. SBI_EXT_ANDES_ICACHE_OP,
  43. SBI_EXT_ANDES_DCACHE_OP,
  44. SBI_EXT_ANDES_L1CACHE_I_PREFETCH,
  45. SBI_EXT_ANDES_L1CACHE_D_PREFETCH,
  46. SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE,
  47. SBI_EXT_ANDES_WRITE_AROUND,
  48. };
  49. /* nds v5 mmisc_ctl register*/
  50. #define V5_MMISC_CTL_VEC_PLIC_OFFSET 1
  51. #define V5_MMISC_CTL_RVCOMPM_OFFSET 2
  52. #define V5_MMISC_CTL_BRPE_OFFSET 3
  53. #define V5_MMISC_CTL_MSA_OR_UNA_OFFSET 6
  54. #define V5_MMISC_CTL_NON_BLOCKING_OFFSET 8
  55. #define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET 9
  56. #define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET 10
  57. #define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1 13
  58. #define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2 14
  59. #define V5_MMISC_CTL_VEC_PLIC_EN (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
  60. #define V5_MMISC_CTL_RVCOMPM_EN (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
  61. #define V5_MMISC_CTL_BRPE_EN (1UL << V5_MMISC_CTL_BRPE_OFFSET)
  62. #define V5_MMISC_CTL_MSA_OR_UNA_EN (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
  63. #define V5_MMISC_CTL_NON_BLOCKING_EN (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
  64. #define V5_MCACHE_CTL_L1I_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
  65. #define V5_MCACHE_CTL_L1D_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
  66. #define V5_MCACHE_CTL_DC_WAROUND_1_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
  67. #define V5_MCACHE_CTL_DC_WAROUND_2_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
  68. #define V5_MMISC_CTL_MASK (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \
  69. | V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN)
  70. /* nds mcache_ctl register*/
  71. #define V5_MCACHE_CTL_IC_EN_OFFSET 0
  72. #define V5_MCACHE_CTL_DC_EN_OFFSET 1
  73. #define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2
  74. #define V5_MCACHE_CTL_DC_ECCEN_OFFSET 4
  75. #define V5_MCACHE_CTL_IC_RWECC_OFFSET 6
  76. #define V5_MCACHE_CTL_DC_RWECC_OFFSET 7
  77. #define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
  78. /*nds cctl command*/
  79. #define V5_UCCTL_L1D_WBINVAL_ALL 6
  80. #define V5_UCCTL_L1D_WB_ALL 7
  81. #define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
  82. #define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
  83. #define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
  84. #define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
  85. #define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
  86. #define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \
  87. | V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \
  88. | V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \
  89. | V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \
  90. | V5_MCACHE_CTL_DC_WAROUND_2_EN)
  91. #define V5_L2C_CTL_OFFSET 0x8
  92. #define V5_L2C_CTL_ENABLE_OFFSET 0
  93. #define V5_L2C_CTL_IPFDPT_OFFSET 3
  94. #define V5_L2C_CTL_DPFDPT_OFFSET 5
  95. #define V5_L2C_CTL_TRAMOCTL_OFFSET 8
  96. #define V5_L2C_CTL_TRAMICTL_OFFSET 10
  97. #define V5_L2C_CTL_DRAMOCTL_OFFSET 11
  98. #define V5_L2C_CTL_DRAMICTL_OFFSET 13
  99. #define V5_L2C_CTL_ENABLE_MASK (1UL << V5_L2C_CTL_ENABLE_OFFSET)
  100. #define V5_L2C_CTL_IPFDPT_MASK (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
  101. #define V5_L2C_CTL_DPFDPT_MASK (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
  102. #define V5_L2C_CTL_TRAMOCTL_MASK (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
  103. #define V5_L2C_CTL_TRAMICTL_MASK (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
  104. #define V5_L2C_CTL_DRAMOCTL_MASK (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
  105. #define V5_L2C_CTL_DRAMICTL_MASK (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
  106. #endif /* _AE350_PLATFORM_H_ */