0005-base-allocator-partition_allocator-add-riscv64-suppo.patch 4.3 KB

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  1. From 3a0f884a18211957feb88fd6ee650c75051e3c8e Mon Sep 17 00:00:00 2001
  2. From: Rebecca Chang Swee Fun <rebecca.chang@starfivetech.com>
  3. Date: Tue, 5 Apr 2022 02:22:48 +0000
  4. Subject: [PATCH 05/22] base: allocator: partition_allocator: add riscv64
  5. support
  6. Signed-off-by: Rebecca Chang Swee Fun <rebecca.chang@starfivetech.com>
  7. ---
  8. base/allocator/partition_allocator/BUILD.gn | 3 ++
  9. .../stack/asm/riscv64/push_registers_asm.cc | 51 +++++++++++++++++++
  10. 2 files changed, 54 insertions(+)
  11. create mode 100644 base/allocator/partition_allocator/starscan/stack/asm/riscv64/push_registers_asm.cc
  12. diff --git a/base/allocator/partition_allocator/BUILD.gn b/base/allocator/partition_allocator/BUILD.gn
  13. index d8272085d9676..262a57bcbc209 100644
  14. --- a/base/allocator/partition_allocator/BUILD.gn
  15. +++ b/base/allocator/partition_allocator/BUILD.gn
  16. @@ -225,6 +225,9 @@ target(partition_alloc_target_type, "partition_alloc") {
  17. } else if (current_cpu == "arm64") {
  18. defines += [ "PA_PCSCAN_STACK_SUPPORTED" ]
  19. sources += [ "starscan/stack/asm/arm64/push_registers_asm.cc" ]
  20. + } else if (current_cpu == "riscv64") {
  21. + defines += [ "PA_PCSCAN_STACK_SUPPORTED" ]
  22. + sources += [ "starscan/stack/asm/riscv64/push_registers_asm.cc" ]
  23. } else {
  24. # To support a trampoline for another arch, please refer to v8/src/heap/base.
  25. }
  26. diff --git a/base/allocator/partition_allocator/starscan/stack/asm/riscv64/push_registers_asm.cc b/base/allocator/partition_allocator/starscan/stack/asm/riscv64/push_registers_asm.cc
  27. new file mode 100644
  28. index 0000000000000..2d90aab182988
  29. --- /dev/null
  30. +++ b/base/allocator/partition_allocator/starscan/stack/asm/riscv64/push_registers_asm.cc
  31. @@ -0,0 +1,51 @@
  32. +// Copyright 2020 the V8 project authors. All rights reserved.
  33. +// Use of this source code is governed by a BSD-style license that can be
  34. +// found in the LICENSE file.
  35. +
  36. +// Push all callee-saved registers to get them on the stack for conservative
  37. +// stack scanning.
  38. +//
  39. +// See asm/x64/push_registers_asm.cc for why the function is not generated
  40. +// using clang.
  41. +//
  42. +// Calling convention source:
  43. +// https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf Table 18.2
  44. +asm(".global PushAllRegistersAndIterateStack \n"
  45. + ".type PushAllRegistersAndIterateStack, %function \n"
  46. + ".hidden PushAllRegistersAndIterateStack \n"
  47. + "PushAllRegistersAndIterateStack: \n"
  48. + // Push all callee-saved registers and save return address.
  49. + " addi sp, sp, -112 \n"
  50. + // Save return address.
  51. + " sd ra, 104(sp) \n"
  52. + // sp is callee-saved.
  53. + " sd sp, 96(sp) \n"
  54. + // s0-s11 are callee-saved.
  55. + " sd s11, 88(sp) \n"
  56. + " sd s10, 80(sp) \n"
  57. + " sd s9, 72(sp) \n"
  58. + " sd s8, 64(sp) \n"
  59. + " sd s7, 56(sp) \n"
  60. + " sd s6, 48(sp) \n"
  61. + " sd s5, 40(sp) \n"
  62. + " sd s4, 32(sp) \n"
  63. + " sd s3, 24(sp) \n"
  64. + " sd s2, 16(sp) \n"
  65. + " sd s1, 8(sp) \n"
  66. + " sd s0, 0(sp) \n"
  67. + // Maintain frame pointer(fp is s0).
  68. + " mv s0, sp \n"
  69. + // Pass 1st parameter (a0) unchanged (Stack*).
  70. + // Pass 2nd parameter (a1) unchanged (StackVisitor*).
  71. + // Save 3rd parameter (a2; IterateStackCallback) to a3.
  72. + " mv a3, a2 \n"
  73. + // Pass 3rd parameter as sp (stack pointer).
  74. + " mv a2, sp \n"
  75. + // Call the callback.
  76. + " jalr a3 \n"
  77. + // Load return address.
  78. + " ld ra, 104(sp) \n"
  79. + // Restore frame pointer.
  80. + " ld s0, 0(sp) \n"
  81. + " addi sp, sp, 112 \n"
  82. + " jr ra \n");
  83. --
  84. 2.25.1