aclint_mtimer.c 5.9 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_atomic.h>
  11. #include <sbi/riscv_io.h>
  12. #include <sbi/sbi_bitops.h>
  13. #include <sbi/sbi_domain.h>
  14. #include <sbi/sbi_error.h>
  15. #include <sbi/sbi_hartmask.h>
  16. #include <sbi/sbi_ipi.h>
  17. #include <sbi/sbi_timer.h>
  18. #include <sbi_utils/timer/aclint_mtimer.h>
  19. static struct aclint_mtimer_data *mtimer_hartid2data[SBI_HARTMASK_MAX_BITS];
  20. #if __riscv_xlen != 32
  21. static u64 mtimer_time_rd64(volatile u64 *addr)
  22. {
  23. return readq_relaxed(addr);
  24. }
  25. static void mtimer_time_wr64(bool timecmp, u64 value, volatile u64 *addr)
  26. {
  27. writeq_relaxed(value, addr);
  28. }
  29. #endif
  30. static u64 mtimer_time_rd32(volatile u64 *addr)
  31. {
  32. u32 lo, hi;
  33. do {
  34. hi = readl_relaxed((u32 *)addr + 1);
  35. lo = readl_relaxed((u32 *)addr);
  36. } while (hi != readl_relaxed((u32 *)addr + 1));
  37. return ((u64)hi << 32) | (u64)lo;
  38. }
  39. static void mtimer_time_wr32(bool timecmp, u64 value, volatile u64 *addr)
  40. {
  41. writel_relaxed((timecmp) ? -1U : 0U, (void *)(addr));
  42. writel_relaxed((u32)(value >> 32), (char *)(addr) + 0x04);
  43. writel_relaxed((u32)value, (void *)(addr));
  44. }
  45. static u64 mtimer_value(void)
  46. {
  47. struct aclint_mtimer_data *mt = mtimer_hartid2data[current_hartid()];
  48. u64 *time_val = (void *)mt->mtime_addr;
  49. /* Read MTIMER Time Value */
  50. return mt->time_rd(time_val);
  51. }
  52. static void mtimer_event_stop(void)
  53. {
  54. u32 target_hart = current_hartid();
  55. struct aclint_mtimer_data *mt = mtimer_hartid2data[target_hart];
  56. u64 *time_cmp = (void *)mt->mtimecmp_addr;
  57. /* Clear MTIMER Time Compare */
  58. mt->time_wr(true, -1ULL, &time_cmp[target_hart - mt->first_hartid]);
  59. }
  60. static void mtimer_event_start(u64 next_event)
  61. {
  62. u32 target_hart = current_hartid();
  63. struct aclint_mtimer_data *mt = mtimer_hartid2data[target_hart];
  64. u64 *time_cmp = (void *)mt->mtimecmp_addr;
  65. /* Program MTIMER Time Compare */
  66. mt->time_wr(true, next_event,
  67. &time_cmp[target_hart - mt->first_hartid]);
  68. }
  69. static struct sbi_timer_device mtimer = {
  70. .name = "aclint-mtimer",
  71. .timer_value = mtimer_value,
  72. .timer_event_start = mtimer_event_start,
  73. .timer_event_stop = mtimer_event_stop
  74. };
  75. void aclint_mtimer_sync(struct aclint_mtimer_data *mt)
  76. {
  77. u64 v1, v2, mv, delta;
  78. u64 *mt_time_val, *ref_time_val;
  79. struct aclint_mtimer_data *reference;
  80. /* Sync-up non-shared MTIME if reference is available */
  81. if (mt->has_shared_mtime || !mt->time_delta_reference)
  82. return;
  83. reference = mt->time_delta_reference;
  84. mt_time_val = (void *)mt->mtime_addr;
  85. ref_time_val = (void *)reference->mtime_addr;
  86. if (!atomic_raw_xchg_ulong(&mt->time_delta_computed, 1)) {
  87. v1 = mt->time_rd(mt_time_val);
  88. mv = reference->time_rd(ref_time_val);
  89. v2 = mt->time_rd(mt_time_val);
  90. delta = mv - ((v1 / 2) + (v2 / 2));
  91. mt->time_wr(false, mt->time_rd(mt_time_val) + delta,
  92. mt_time_val);
  93. }
  94. }
  95. void aclint_mtimer_set_reference(struct aclint_mtimer_data *mt,
  96. struct aclint_mtimer_data *ref)
  97. {
  98. if (!mt || !ref || mt == ref)
  99. return;
  100. mt->time_delta_reference = ref;
  101. mt->time_delta_computed = 0;
  102. }
  103. int aclint_mtimer_warm_init(void)
  104. {
  105. u64 *mt_time_cmp;
  106. u32 target_hart = current_hartid();
  107. struct aclint_mtimer_data *mt = mtimer_hartid2data[target_hart];
  108. if (!mt)
  109. return SBI_ENODEV;
  110. /* Sync-up MTIME register */
  111. aclint_mtimer_sync(mt);
  112. /* Clear Time Compare */
  113. mt_time_cmp = (void *)mt->mtimecmp_addr;
  114. mt->time_wr(true, -1ULL,
  115. &mt_time_cmp[target_hart - mt->first_hartid]);
  116. return 0;
  117. }
  118. int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
  119. struct aclint_mtimer_data *reference)
  120. {
  121. u32 i;
  122. int rc;
  123. /* Sanity checks */
  124. if (!mt ||
  125. (mt->hart_count && !mt->mtimecmp_size) ||
  126. (mt->mtime_size && (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1))) ||
  127. (mt->mtime_size && (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1))) ||
  128. (mt->mtimecmp_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
  129. (mt->mtimecmp_size & (ACLINT_MTIMER_ALIGN - 1)) ||
  130. (mt->first_hartid >= SBI_HARTMASK_MAX_BITS) ||
  131. (mt->hart_count > ACLINT_MTIMER_MAX_HARTS))
  132. return SBI_EINVAL;
  133. if (reference && mt->mtime_freq != reference->mtime_freq)
  134. return SBI_EINVAL;
  135. /* Initialize private data */
  136. aclint_mtimer_set_reference(mt, reference);
  137. mt->time_rd = mtimer_time_rd32;
  138. mt->time_wr = mtimer_time_wr32;
  139. /* Override read/write accessors for 64bit MMIO */
  140. #if __riscv_xlen != 32
  141. if (mt->has_64bit_mmio) {
  142. mt->time_rd = mtimer_time_rd64;
  143. mt->time_wr = mtimer_time_wr64;
  144. }
  145. #endif
  146. /* Update MTIMER hartid table */
  147. for (i = 0; i < mt->hart_count; i++)
  148. mtimer_hartid2data[mt->first_hartid + i] = mt;
  149. if (!mt->mtime_size) {
  150. /* Disable reading mtime when mtime is not available */
  151. mtimer.timer_value = NULL;
  152. }
  153. /* Add MTIMER regions to the root domain */
  154. if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) {
  155. rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
  156. mt->mtime_size + mt->mtimecmp_size,
  157. MTIMER_REGION_ALIGN,
  158. (SBI_DOMAIN_MEMREGION_MMIO |
  159. SBI_DOMAIN_MEMREGION_M_READABLE |
  160. SBI_DOMAIN_MEMREGION_M_WRITABLE));
  161. if (rc)
  162. return rc;
  163. } else if (mt->mtimecmp_addr == (mt->mtime_addr + mt->mtime_size)) {
  164. rc = sbi_domain_root_add_memrange(mt->mtime_addr,
  165. mt->mtime_size + mt->mtimecmp_size,
  166. MTIMER_REGION_ALIGN,
  167. (SBI_DOMAIN_MEMREGION_MMIO |
  168. SBI_DOMAIN_MEMREGION_M_READABLE |
  169. SBI_DOMAIN_MEMREGION_M_WRITABLE));
  170. if (rc)
  171. return rc;
  172. } else {
  173. rc = sbi_domain_root_add_memrange(mt->mtime_addr,
  174. mt->mtime_size, MTIMER_REGION_ALIGN,
  175. (SBI_DOMAIN_MEMREGION_MMIO |
  176. SBI_DOMAIN_MEMREGION_M_READABLE |
  177. SBI_DOMAIN_MEMREGION_M_WRITABLE));
  178. if (rc)
  179. return rc;
  180. rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
  181. mt->mtimecmp_size, MTIMER_REGION_ALIGN,
  182. (SBI_DOMAIN_MEMREGION_MMIO |
  183. SBI_DOMAIN_MEMREGION_M_READABLE |
  184. SBI_DOMAIN_MEMREGION_M_WRITABLE));
  185. if (rc)
  186. return rc;
  187. }
  188. mtimer.timer_freq = mt->mtime_freq;
  189. sbi_timer_set_device(&mtimer);
  190. return 0;
  191. }