renesas_scif.c 3.0 KB

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  1. // SPDX-License-Identifier: BSD-2-Clause
  2. /*
  3. * Copyright (C) 2022 Renesas Electronics Corporation
  4. */
  5. #include <sbi/riscv_io.h>
  6. #include <sbi/sbi_console.h>
  7. #include <sbi/sbi_timer.h>
  8. #include <sbi_utils/serial/renesas-scif.h>
  9. /* clang-format off */
  10. #define SCIF_REG_SMR 0x0
  11. #define SCIF_REG_BRR 0x2
  12. #define SCIF_REG_SCR 0x4
  13. #define SCIF_REG_FTDR 0x6
  14. #define SCIF_REG_FSR 0x8
  15. #define SCIF_REG_FCR 0xc
  16. #define SCIF_REG_LSR 0x12
  17. #define SCIF_REG_SEMR 0x14
  18. #define SCIF_FCR_RFRST 0x2 /* Reset assert receive-FIFO (bit[1]) */
  19. #define SCIF_FCR_TFRST 0x4 /* Reset assert transmit-FIFO(bit[2]) */
  20. #define SCIF_FCR_RST_ASSRT_RFTF (SCIF_FCR_RFRST | SCIF_FCR_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
  21. #define SCIF_FCR_RST_NGATE_RFTF 0x0 /* Reset negate tx-FIFO & rx-FIFO */
  22. #define SCIF_SCR_RE 0x10 /* Enable receive (bit[4]) */
  23. #define SCIF_SCR_TE 0x20 /* Enable transmit(bit[5]) */
  24. #define SCIF_SCR_RCV_TRN_EN (SCIF_SCR_RE | SCIF_SCR_TE) /* Enable receive & transmit */
  25. #define SCIF_SCR_RCV_TRN_DIS 0x0 /* Disable receive & transmit */
  26. #define SCIF_FSR_ER 0x80 /* Receive error flag */
  27. #define SCIF_FSR_TEND 0x40 /* Transmit End Flag */
  28. #define SCIF_FSR_TDFE 0x20 /* Transmit FIFO Data Empty Flag */
  29. #define SCIF_FSR_BRK 0x10 /* Detect break flag */
  30. #define SCIF_FSR_DR 0x1 /* Receive data ready flag */
  31. #define SCIF_FSR_TXD_CHK (SCIF_FSR_TEND | SCIF_FSR_TDFE)
  32. #define SCIF_SEMR_MDDRS 0x10 /* MDDR access enable */
  33. #define SCIF_REG_8BIT(reg) ((reg == SCIF_REG_BRR) || \
  34. (reg == SCIF_REG_FTDR) || \
  35. (reg == SCIF_REG_SEMR))
  36. #define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
  37. /* clang-format on */
  38. static volatile char *scif_base;
  39. static u32 get_reg(u32 offset)
  40. {
  41. if (SCIF_REG_8BIT(offset))
  42. return readb(scif_base + offset);
  43. return readw(scif_base + offset);
  44. }
  45. static void set_reg(u32 offset, u32 val)
  46. {
  47. if (SCIF_REG_8BIT(offset))
  48. writeb(val, scif_base + offset);
  49. else
  50. writew(val, scif_base + offset);
  51. }
  52. static void renesas_scif_putc(char ch)
  53. {
  54. uint16_t reg;
  55. while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
  56. ;
  57. set_reg(SCIF_REG_FTDR, ch);
  58. reg = get_reg(SCIF_REG_FSR);
  59. reg &= ~SCIF_FSR_TXD_CHK;
  60. set_reg(SCIF_REG_FSR, reg);
  61. }
  62. static struct sbi_console_device renesas_scif_console = {
  63. .name = "renesas_scif",
  64. .console_putc = renesas_scif_putc,
  65. };
  66. int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
  67. {
  68. uint16_t data16;
  69. scif_base = (volatile char *)base;
  70. set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS);
  71. set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF);
  72. data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
  73. set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
  74. data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
  75. set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
  76. set_reg(SCIF_REG_SCR, 0x0);
  77. set_reg(SCIF_REG_SMR, 0x0);
  78. data16 = get_reg(SCIF_REG_SEMR);
  79. set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS));
  80. set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
  81. set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF);
  82. set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN);
  83. sbi_console_set_device(&renesas_scif_console);
  84. return 0;
  85. }