sbi_tlb.c 11 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. * Anup Patel <anup.patel@wdc.com>
  9. */
  10. #include <sbi/riscv_asm.h>
  11. #include <sbi/riscv_atomic.h>
  12. #include <sbi/riscv_barrier.h>
  13. #include <sbi/sbi_error.h>
  14. #include <sbi/sbi_fifo.h>
  15. #include <sbi/sbi_hart.h>
  16. #include <sbi/sbi_ipi.h>
  17. #include <sbi/sbi_scratch.h>
  18. #include <sbi/sbi_tlb.h>
  19. #include <sbi/sbi_hfence.h>
  20. #include <sbi/sbi_string.h>
  21. #include <sbi/sbi_console.h>
  22. #include <sbi/sbi_platform.h>
  23. #include <sbi/sbi_pmu.h>
  24. static unsigned long tlb_sync_off;
  25. static unsigned long tlb_fifo_off;
  26. static unsigned long tlb_fifo_mem_off;
  27. static unsigned long tlb_range_flush_limit;
  28. static void tlb_flush_all(void)
  29. {
  30. __asm__ __volatile("sfence.vma");
  31. }
  32. void sbi_tlb_local_hfence_vvma(struct sbi_tlb_info *tinfo)
  33. {
  34. unsigned long start = tinfo->start;
  35. unsigned long size = tinfo->size;
  36. unsigned long vmid = tinfo->vmid;
  37. unsigned long i, hgatp;
  38. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_RCVD);
  39. hgatp = csr_swap(CSR_HGATP,
  40. (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
  41. if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
  42. __sbi_hfence_vvma_all();
  43. goto done;
  44. }
  45. for (i = 0; i < size; i += PAGE_SIZE) {
  46. __sbi_hfence_vvma_va(start+i);
  47. }
  48. done:
  49. csr_write(CSR_HGATP, hgatp);
  50. }
  51. void sbi_tlb_local_hfence_gvma(struct sbi_tlb_info *tinfo)
  52. {
  53. unsigned long start = tinfo->start;
  54. unsigned long size = tinfo->size;
  55. unsigned long i;
  56. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_RCVD);
  57. if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
  58. __sbi_hfence_gvma_all();
  59. return;
  60. }
  61. for (i = 0; i < size; i += PAGE_SIZE) {
  62. __sbi_hfence_gvma_gpa((start + i) >> 2);
  63. }
  64. }
  65. void sbi_tlb_local_sfence_vma(struct sbi_tlb_info *tinfo)
  66. {
  67. unsigned long start = tinfo->start;
  68. unsigned long size = tinfo->size;
  69. unsigned long i;
  70. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_RCVD);
  71. if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
  72. tlb_flush_all();
  73. return;
  74. }
  75. for (i = 0; i < size; i += PAGE_SIZE) {
  76. __asm__ __volatile__("sfence.vma %0"
  77. :
  78. : "r"(start + i)
  79. : "memory");
  80. }
  81. }
  82. void sbi_tlb_local_hfence_vvma_asid(struct sbi_tlb_info *tinfo)
  83. {
  84. unsigned long start = tinfo->start;
  85. unsigned long size = tinfo->size;
  86. unsigned long asid = tinfo->asid;
  87. unsigned long vmid = tinfo->vmid;
  88. unsigned long i, hgatp;
  89. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD);
  90. hgatp = csr_swap(CSR_HGATP,
  91. (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
  92. if (start == 0 && size == 0) {
  93. __sbi_hfence_vvma_all();
  94. goto done;
  95. }
  96. if (size == SBI_TLB_FLUSH_ALL) {
  97. __sbi_hfence_vvma_asid(asid);
  98. goto done;
  99. }
  100. for (i = 0; i < size; i += PAGE_SIZE) {
  101. __sbi_hfence_vvma_asid_va(start + i, asid);
  102. }
  103. done:
  104. csr_write(CSR_HGATP, hgatp);
  105. }
  106. void sbi_tlb_local_hfence_gvma_vmid(struct sbi_tlb_info *tinfo)
  107. {
  108. unsigned long start = tinfo->start;
  109. unsigned long size = tinfo->size;
  110. unsigned long vmid = tinfo->vmid;
  111. unsigned long i;
  112. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD);
  113. if (start == 0 && size == 0) {
  114. __sbi_hfence_gvma_all();
  115. return;
  116. }
  117. if (size == SBI_TLB_FLUSH_ALL) {
  118. __sbi_hfence_gvma_vmid(vmid);
  119. return;
  120. }
  121. for (i = 0; i < size; i += PAGE_SIZE) {
  122. __sbi_hfence_gvma_vmid_gpa((start + i) >> 2, vmid);
  123. }
  124. }
  125. void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo)
  126. {
  127. unsigned long start = tinfo->start;
  128. unsigned long size = tinfo->size;
  129. unsigned long asid = tinfo->asid;
  130. unsigned long i;
  131. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_ASID_RCVD);
  132. if (start == 0 && size == 0) {
  133. tlb_flush_all();
  134. return;
  135. }
  136. /* Flush entire MM context for a given ASID */
  137. if (size == SBI_TLB_FLUSH_ALL) {
  138. __asm__ __volatile__("sfence.vma x0, %0"
  139. :
  140. : "r"(asid)
  141. : "memory");
  142. return;
  143. }
  144. for (i = 0; i < size; i += PAGE_SIZE) {
  145. __asm__ __volatile__("sfence.vma %0, %1"
  146. :
  147. : "r"(start + i), "r"(asid)
  148. : "memory");
  149. }
  150. }
  151. void sbi_tlb_local_fence_i(struct sbi_tlb_info *tinfo)
  152. {
  153. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_FENCE_I_RECVD);
  154. __asm__ __volatile("fence.i");
  155. }
  156. static void tlb_pmu_incr_fw_ctr(struct sbi_tlb_info *data)
  157. {
  158. if (unlikely(!data))
  159. return;
  160. if (data->local_fn == sbi_tlb_local_fence_i)
  161. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_FENCE_I_SENT);
  162. else if (data->local_fn == sbi_tlb_local_sfence_vma)
  163. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_SENT);
  164. else if (data->local_fn == sbi_tlb_local_sfence_vma_asid)
  165. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_ASID_SENT);
  166. else if (data->local_fn == sbi_tlb_local_hfence_gvma)
  167. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_SENT);
  168. else if (data->local_fn == sbi_tlb_local_hfence_gvma_vmid)
  169. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_VMID_SENT);
  170. else if (data->local_fn == sbi_tlb_local_hfence_vvma)
  171. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_SENT);
  172. else if (data->local_fn == sbi_tlb_local_hfence_vvma_asid)
  173. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_ASID_SENT);
  174. }
  175. static void tlb_entry_process(struct sbi_tlb_info *tinfo)
  176. {
  177. u32 rhartid;
  178. struct sbi_scratch *rscratch = NULL;
  179. unsigned long *rtlb_sync = NULL;
  180. tinfo->local_fn(tinfo);
  181. sbi_hartmask_for_each_hart(rhartid, &tinfo->smask) {
  182. rscratch = sbi_hartid_to_scratch(rhartid);
  183. if (!rscratch)
  184. continue;
  185. rtlb_sync = sbi_scratch_offset_ptr(rscratch, tlb_sync_off);
  186. while (atomic_raw_xchg_ulong(rtlb_sync, 1)) ;
  187. }
  188. }
  189. static void tlb_process_count(struct sbi_scratch *scratch, int count)
  190. {
  191. struct sbi_tlb_info tinfo;
  192. unsigned int deq_count = 0;
  193. struct sbi_fifo *tlb_fifo =
  194. sbi_scratch_offset_ptr(scratch, tlb_fifo_off);
  195. while (!sbi_fifo_dequeue(tlb_fifo, &tinfo)) {
  196. tlb_entry_process(&tinfo);
  197. deq_count++;
  198. if (deq_count > count)
  199. break;
  200. }
  201. }
  202. static void tlb_process(struct sbi_scratch *scratch)
  203. {
  204. struct sbi_tlb_info tinfo;
  205. struct sbi_fifo *tlb_fifo =
  206. sbi_scratch_offset_ptr(scratch, tlb_fifo_off);
  207. while (!sbi_fifo_dequeue(tlb_fifo, &tinfo))
  208. tlb_entry_process(&tinfo);
  209. }
  210. static void tlb_sync(struct sbi_scratch *scratch)
  211. {
  212. unsigned long *tlb_sync =
  213. sbi_scratch_offset_ptr(scratch, tlb_sync_off);
  214. while (!atomic_raw_xchg_ulong(tlb_sync, 0)) {
  215. /*
  216. * While we are waiting for remote hart to set the sync,
  217. * consume fifo requests to avoid deadlock.
  218. */
  219. tlb_process_count(scratch, 1);
  220. }
  221. return;
  222. }
  223. static inline int tlb_range_check(struct sbi_tlb_info *curr,
  224. struct sbi_tlb_info *next)
  225. {
  226. unsigned long curr_end;
  227. unsigned long next_end;
  228. int ret = SBI_FIFO_UNCHANGED;
  229. if (!curr || !next)
  230. return ret;
  231. next_end = next->start + next->size;
  232. curr_end = curr->start + curr->size;
  233. if (next->start <= curr->start && next_end > curr_end) {
  234. curr->start = next->start;
  235. curr->size = next->size;
  236. sbi_hartmask_or(&curr->smask, &curr->smask, &next->smask);
  237. ret = SBI_FIFO_UPDATED;
  238. } else if (next->start >= curr->start && next_end <= curr_end) {
  239. sbi_hartmask_or(&curr->smask, &curr->smask, &next->smask);
  240. ret = SBI_FIFO_SKIP;
  241. }
  242. return ret;
  243. }
  244. /**
  245. * Call back to decide if an inplace fifo update is required or next entry can
  246. * can be skipped. Here are the different cases that are being handled.
  247. *
  248. * Case1:
  249. * if next flush request range lies within one of the existing entry, skip
  250. * the next entry.
  251. * Case2:
  252. * if flush request range in current fifo entry lies within next flush
  253. * request, update the current entry.
  254. *
  255. * Note:
  256. * We can not issue a fifo reset anymore if a complete vma flush is requested.
  257. * This is because we are queueing FENCE.I requests as well now.
  258. * To ease up the pressure in enqueue/fifo sync path, try to dequeue 1 element
  259. * before continuing the while loop. This method is preferred over wfi/ipi because
  260. * of MMIO cost involved in later method.
  261. */
  262. static int tlb_update_cb(void *in, void *data)
  263. {
  264. struct sbi_tlb_info *curr;
  265. struct sbi_tlb_info *next;
  266. int ret = SBI_FIFO_UNCHANGED;
  267. if (!in || !data)
  268. return ret;
  269. curr = (struct sbi_tlb_info *)data;
  270. next = (struct sbi_tlb_info *)in;
  271. if (next->local_fn == sbi_tlb_local_sfence_vma_asid &&
  272. curr->local_fn == sbi_tlb_local_sfence_vma_asid) {
  273. if (next->asid == curr->asid)
  274. ret = tlb_range_check(curr, next);
  275. } else if (next->local_fn == sbi_tlb_local_sfence_vma &&
  276. curr->local_fn == sbi_tlb_local_sfence_vma) {
  277. ret = tlb_range_check(curr, next);
  278. }
  279. return ret;
  280. }
  281. static int tlb_update(struct sbi_scratch *scratch,
  282. struct sbi_scratch *remote_scratch,
  283. u32 remote_hartid, void *data)
  284. {
  285. int ret;
  286. struct sbi_fifo *tlb_fifo_r;
  287. struct sbi_tlb_info *tinfo = data;
  288. u32 curr_hartid = current_hartid();
  289. /*
  290. * If address range to flush is too big then simply
  291. * upgrade it to flush all because we can only flush
  292. * 4KB at a time.
  293. */
  294. if (tinfo->size > tlb_range_flush_limit) {
  295. tinfo->start = 0;
  296. tinfo->size = SBI_TLB_FLUSH_ALL;
  297. }
  298. /*
  299. * If the request is to queue a tlb flush entry for itself
  300. * then just do a local flush and return;
  301. */
  302. if (remote_hartid == curr_hartid) {
  303. tinfo->local_fn(tinfo);
  304. return -1;
  305. }
  306. tlb_fifo_r = sbi_scratch_offset_ptr(remote_scratch, tlb_fifo_off);
  307. ret = sbi_fifo_inplace_update(tlb_fifo_r, data, tlb_update_cb);
  308. if (ret != SBI_FIFO_UNCHANGED) {
  309. return 1;
  310. }
  311. while (sbi_fifo_enqueue(tlb_fifo_r, data) < 0) {
  312. /**
  313. * For now, Busy loop until there is space in the fifo.
  314. * There may be case where target hart is also
  315. * enqueue in source hart's fifo. Both hart may busy
  316. * loop leading to a deadlock.
  317. * TODO: Introduce a wait/wakeup event mechanism to handle
  318. * this properly.
  319. */
  320. tlb_process_count(scratch, 1);
  321. sbi_dprintf("hart%d: hart%d tlb fifo full\n",
  322. curr_hartid, remote_hartid);
  323. }
  324. return 0;
  325. }
  326. static struct sbi_ipi_event_ops tlb_ops = {
  327. .name = "IPI_TLB",
  328. .update = tlb_update,
  329. .sync = tlb_sync,
  330. .process = tlb_process,
  331. };
  332. static u32 tlb_event = SBI_IPI_EVENT_MAX;
  333. int sbi_tlb_request(ulong hmask, ulong hbase, struct sbi_tlb_info *tinfo)
  334. {
  335. if (!tinfo->local_fn)
  336. return SBI_EINVAL;
  337. tlb_pmu_incr_fw_ctr(tinfo);
  338. return sbi_ipi_send_many(hmask, hbase, tlb_event, tinfo);
  339. }
  340. int sbi_tlb_init(struct sbi_scratch *scratch, bool cold_boot)
  341. {
  342. int ret;
  343. void *tlb_mem;
  344. unsigned long *tlb_sync;
  345. struct sbi_fifo *tlb_q;
  346. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  347. if (cold_boot) {
  348. tlb_sync_off = sbi_scratch_alloc_offset(sizeof(*tlb_sync));
  349. if (!tlb_sync_off)
  350. return SBI_ENOMEM;
  351. tlb_fifo_off = sbi_scratch_alloc_offset(sizeof(*tlb_q));
  352. if (!tlb_fifo_off) {
  353. sbi_scratch_free_offset(tlb_sync_off);
  354. return SBI_ENOMEM;
  355. }
  356. tlb_fifo_mem_off = sbi_scratch_alloc_offset(
  357. SBI_TLB_FIFO_NUM_ENTRIES * SBI_TLB_INFO_SIZE);
  358. if (!tlb_fifo_mem_off) {
  359. sbi_scratch_free_offset(tlb_fifo_off);
  360. sbi_scratch_free_offset(tlb_sync_off);
  361. return SBI_ENOMEM;
  362. }
  363. ret = sbi_ipi_event_create(&tlb_ops);
  364. if (ret < 0) {
  365. sbi_scratch_free_offset(tlb_fifo_mem_off);
  366. sbi_scratch_free_offset(tlb_fifo_off);
  367. sbi_scratch_free_offset(tlb_sync_off);
  368. return ret;
  369. }
  370. tlb_event = ret;
  371. tlb_range_flush_limit = sbi_platform_tlbr_flush_limit(plat);
  372. } else {
  373. if (!tlb_sync_off ||
  374. !tlb_fifo_off ||
  375. !tlb_fifo_mem_off)
  376. return SBI_ENOMEM;
  377. if (SBI_IPI_EVENT_MAX <= tlb_event)
  378. return SBI_ENOSPC;
  379. }
  380. tlb_sync = sbi_scratch_offset_ptr(scratch, tlb_sync_off);
  381. tlb_q = sbi_scratch_offset_ptr(scratch, tlb_fifo_off);
  382. tlb_mem = sbi_scratch_offset_ptr(scratch, tlb_fifo_mem_off);
  383. *tlb_sync = 0;
  384. sbi_fifo_init(tlb_q, tlb_mem,
  385. SBI_TLB_FIFO_NUM_ENTRIES, SBI_TLB_INFO_SIZE);
  386. return 0;
  387. }