riscv_asm.c 9.3 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_encoding.h>
  11. #include <sbi/sbi_error.h>
  12. #include <sbi/sbi_platform.h>
  13. #include <sbi/sbi_console.h>
  14. /* determine CPU extension, return non-zero support */
  15. int misa_extension_imp(char ext)
  16. {
  17. unsigned long misa = csr_read(CSR_MISA);
  18. if (misa) {
  19. if ('A' <= ext && ext <= 'Z')
  20. return misa & (1 << (ext - 'A'));
  21. if ('a' <= ext && ext <= 'z')
  22. return misa & (1 << (ext - 'a'));
  23. return 0;
  24. }
  25. return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
  26. }
  27. int misa_xlen(void)
  28. {
  29. long r;
  30. if (csr_read(CSR_MISA) == 0)
  31. return sbi_platform_misa_xlen(sbi_platform_thishart_ptr());
  32. __asm__ __volatile__(
  33. "csrr t0, misa\n\t"
  34. "slti t1, t0, 0\n\t"
  35. "slli t1, t1, 1\n\t"
  36. "slli t0, t0, 1\n\t"
  37. "slti t0, t0, 0\n\t"
  38. "add %0, t0, t1"
  39. : "=r"(r)
  40. :
  41. : "t0", "t1");
  42. return r ? r : -1;
  43. }
  44. void misa_string(int xlen, char *out, unsigned int out_sz)
  45. {
  46. unsigned int i, pos = 0;
  47. const char valid_isa_order[] = "iemafdqclbjtpvnhkorwxyzg";
  48. if (!out)
  49. return;
  50. if (5 <= (out_sz - pos)) {
  51. out[pos++] = 'r';
  52. out[pos++] = 'v';
  53. switch (xlen) {
  54. case 1:
  55. out[pos++] = '3';
  56. out[pos++] = '2';
  57. break;
  58. case 2:
  59. out[pos++] = '6';
  60. out[pos++] = '4';
  61. break;
  62. case 3:
  63. out[pos++] = '1';
  64. out[pos++] = '2';
  65. out[pos++] = '8';
  66. break;
  67. default:
  68. sbi_panic("%s: Unknown misa.MXL encoding %d",
  69. __func__, xlen);
  70. return;
  71. }
  72. }
  73. for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
  74. if (misa_extension_imp(valid_isa_order[i]))
  75. out[pos++] = valid_isa_order[i];
  76. }
  77. if (pos < out_sz)
  78. out[pos++] = '\0';
  79. }
  80. unsigned long csr_read_num(int csr_num)
  81. {
  82. #define switchcase_csr_read(__csr_num, __val) \
  83. case __csr_num: \
  84. __val = csr_read(__csr_num); \
  85. break;
  86. #define switchcase_csr_read_2(__csr_num, __val) \
  87. switchcase_csr_read(__csr_num + 0, __val) \
  88. switchcase_csr_read(__csr_num + 1, __val)
  89. #define switchcase_csr_read_4(__csr_num, __val) \
  90. switchcase_csr_read_2(__csr_num + 0, __val) \
  91. switchcase_csr_read_2(__csr_num + 2, __val)
  92. #define switchcase_csr_read_8(__csr_num, __val) \
  93. switchcase_csr_read_4(__csr_num + 0, __val) \
  94. switchcase_csr_read_4(__csr_num + 4, __val)
  95. #define switchcase_csr_read_16(__csr_num, __val) \
  96. switchcase_csr_read_8(__csr_num + 0, __val) \
  97. switchcase_csr_read_8(__csr_num + 8, __val)
  98. #define switchcase_csr_read_32(__csr_num, __val) \
  99. switchcase_csr_read_16(__csr_num + 0, __val) \
  100. switchcase_csr_read_16(__csr_num + 16, __val)
  101. #define switchcase_csr_read_64(__csr_num, __val) \
  102. switchcase_csr_read_32(__csr_num + 0, __val) \
  103. switchcase_csr_read_32(__csr_num + 32, __val)
  104. unsigned long ret = 0;
  105. switch (csr_num) {
  106. switchcase_csr_read_16(CSR_PMPCFG0, ret)
  107. switchcase_csr_read_64(CSR_PMPADDR0, ret)
  108. switchcase_csr_read(CSR_MCYCLE, ret)
  109. switchcase_csr_read(CSR_MINSTRET, ret)
  110. switchcase_csr_read(CSR_MHPMCOUNTER3, ret)
  111. switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret)
  112. switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret)
  113. switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret)
  114. switchcase_csr_read(CSR_MCOUNTINHIBIT, ret)
  115. switchcase_csr_read(CSR_MHPMEVENT3, ret)
  116. switchcase_csr_read_4(CSR_MHPMEVENT4, ret)
  117. switchcase_csr_read_8(CSR_MHPMEVENT8, ret)
  118. switchcase_csr_read_16(CSR_MHPMEVENT16, ret)
  119. #if __riscv_xlen == 32
  120. switchcase_csr_read(CSR_MCYCLEH, ret)
  121. switchcase_csr_read(CSR_MINSTRETH, ret)
  122. switchcase_csr_read(CSR_MHPMCOUNTER3H, ret)
  123. switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret)
  124. switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret)
  125. switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret)
  126. /**
  127. * The CSR range MHPMEVENT[3-16]H are available only if sscofpmf
  128. * extension is present. The caller must ensure that.
  129. */
  130. switchcase_csr_read(CSR_MHPMEVENT3H, ret)
  131. switchcase_csr_read_4(CSR_MHPMEVENT4H, ret)
  132. switchcase_csr_read_8(CSR_MHPMEVENT8H, ret)
  133. switchcase_csr_read_16(CSR_MHPMEVENT16H, ret)
  134. #endif
  135. default:
  136. sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
  137. break;
  138. };
  139. return ret;
  140. #undef switchcase_csr_read_64
  141. #undef switchcase_csr_read_32
  142. #undef switchcase_csr_read_16
  143. #undef switchcase_csr_read_8
  144. #undef switchcase_csr_read_4
  145. #undef switchcase_csr_read_2
  146. #undef switchcase_csr_read
  147. }
  148. void csr_write_num(int csr_num, unsigned long val)
  149. {
  150. #define switchcase_csr_write(__csr_num, __val) \
  151. case __csr_num: \
  152. csr_write(__csr_num, __val); \
  153. break;
  154. #define switchcase_csr_write_2(__csr_num, __val) \
  155. switchcase_csr_write(__csr_num + 0, __val) \
  156. switchcase_csr_write(__csr_num + 1, __val)
  157. #define switchcase_csr_write_4(__csr_num, __val) \
  158. switchcase_csr_write_2(__csr_num + 0, __val) \
  159. switchcase_csr_write_2(__csr_num + 2, __val)
  160. #define switchcase_csr_write_8(__csr_num, __val) \
  161. switchcase_csr_write_4(__csr_num + 0, __val) \
  162. switchcase_csr_write_4(__csr_num + 4, __val)
  163. #define switchcase_csr_write_16(__csr_num, __val) \
  164. switchcase_csr_write_8(__csr_num + 0, __val) \
  165. switchcase_csr_write_8(__csr_num + 8, __val)
  166. #define switchcase_csr_write_32(__csr_num, __val) \
  167. switchcase_csr_write_16(__csr_num + 0, __val) \
  168. switchcase_csr_write_16(__csr_num + 16, __val)
  169. #define switchcase_csr_write_64(__csr_num, __val) \
  170. switchcase_csr_write_32(__csr_num + 0, __val) \
  171. switchcase_csr_write_32(__csr_num + 32, __val)
  172. switch (csr_num) {
  173. switchcase_csr_write_16(CSR_PMPCFG0, val)
  174. switchcase_csr_write_64(CSR_PMPADDR0, val)
  175. switchcase_csr_write(CSR_MCYCLE, val)
  176. switchcase_csr_write(CSR_MINSTRET, val)
  177. switchcase_csr_write(CSR_MHPMCOUNTER3, val)
  178. switchcase_csr_write_4(CSR_MHPMCOUNTER4, val)
  179. switchcase_csr_write_8(CSR_MHPMCOUNTER8, val)
  180. switchcase_csr_write_16(CSR_MHPMCOUNTER16, val)
  181. #if __riscv_xlen == 32
  182. switchcase_csr_write(CSR_MCYCLEH, val)
  183. switchcase_csr_write(CSR_MINSTRETH, val)
  184. switchcase_csr_write(CSR_MHPMCOUNTER3H, val)
  185. switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val)
  186. switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val)
  187. switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val)
  188. switchcase_csr_write(CSR_MHPMEVENT3H, val)
  189. switchcase_csr_write_4(CSR_MHPMEVENT4H, val)
  190. switchcase_csr_write_8(CSR_MHPMEVENT8H, val)
  191. switchcase_csr_write_16(CSR_MHPMEVENT16H, val)
  192. #endif
  193. switchcase_csr_write(CSR_MCOUNTINHIBIT, val)
  194. switchcase_csr_write(CSR_MHPMEVENT3, val)
  195. switchcase_csr_write_4(CSR_MHPMEVENT4, val)
  196. switchcase_csr_write_8(CSR_MHPMEVENT8, val)
  197. switchcase_csr_write_16(CSR_MHPMEVENT16, val)
  198. default:
  199. sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
  200. break;
  201. };
  202. #undef switchcase_csr_write_64
  203. #undef switchcase_csr_write_32
  204. #undef switchcase_csr_write_16
  205. #undef switchcase_csr_write_8
  206. #undef switchcase_csr_write_4
  207. #undef switchcase_csr_write_2
  208. #undef switchcase_csr_write
  209. }
  210. static unsigned long ctz(unsigned long x)
  211. {
  212. unsigned long ret = 0;
  213. if (x == 0)
  214. return 8 * sizeof(x);
  215. while (!(x & 1UL)) {
  216. ret++;
  217. x = x >> 1;
  218. }
  219. return ret;
  220. }
  221. int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
  222. unsigned long log2len)
  223. {
  224. int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
  225. unsigned long cfgmask, pmpcfg;
  226. unsigned long addrmask, pmpaddr;
  227. /* check parameters */
  228. if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT)
  229. return SBI_EINVAL;
  230. /* calculate PMP register and offset */
  231. #if __riscv_xlen == 32
  232. pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
  233. pmpcfg_shift = (n & 3) << 3;
  234. #elif __riscv_xlen == 64
  235. pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
  236. pmpcfg_shift = (n & 7) << 3;
  237. #else
  238. # error "Unexpected __riscv_xlen"
  239. #endif
  240. pmpaddr_csr = CSR_PMPADDR0 + n;
  241. /* encode PMP config */
  242. prot &= ~PMP_A;
  243. prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
  244. cfgmask = ~(0xffUL << pmpcfg_shift);
  245. pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
  246. pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
  247. /* encode PMP address */
  248. if (log2len == PMP_SHIFT) {
  249. pmpaddr = (addr >> PMP_SHIFT);
  250. } else {
  251. if (log2len == __riscv_xlen) {
  252. pmpaddr = -1UL;
  253. } else {
  254. addrmask = (1UL << (log2len - PMP_SHIFT)) - 1;
  255. pmpaddr = ((addr >> PMP_SHIFT) & ~addrmask);
  256. pmpaddr |= (addrmask >> 1);
  257. }
  258. }
  259. /* write csrs */
  260. csr_write_num(pmpaddr_csr, pmpaddr);
  261. csr_write_num(pmpcfg_csr, pmpcfg);
  262. return 0;
  263. }
  264. int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
  265. unsigned long *log2len)
  266. {
  267. int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
  268. unsigned long cfgmask, pmpcfg, prot;
  269. unsigned long t1, addr, len;
  270. /* check parameters */
  271. if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len)
  272. return SBI_EINVAL;
  273. *prot_out = *addr_out = *log2len = 0;
  274. /* calculate PMP register and offset */
  275. #if __riscv_xlen == 32
  276. pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
  277. pmpcfg_shift = (n & 3) << 3;
  278. #elif __riscv_xlen == 64
  279. pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
  280. pmpcfg_shift = (n & 7) << 3;
  281. #else
  282. # error "Unexpected __riscv_xlen"
  283. #endif
  284. pmpaddr_csr = CSR_PMPADDR0 + n;
  285. /* decode PMP config */
  286. cfgmask = (0xffUL << pmpcfg_shift);
  287. pmpcfg = csr_read_num(pmpcfg_csr) & cfgmask;
  288. prot = pmpcfg >> pmpcfg_shift;
  289. /* decode PMP address */
  290. if ((prot & PMP_A) == PMP_A_NAPOT) {
  291. addr = csr_read_num(pmpaddr_csr);
  292. if (addr == -1UL) {
  293. addr = 0;
  294. len = __riscv_xlen;
  295. } else {
  296. t1 = ctz(~addr);
  297. addr = (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
  298. len = (t1 + PMP_SHIFT + 1);
  299. }
  300. } else {
  301. addr = csr_read_num(pmpaddr_csr) << PMP_SHIFT;
  302. len = PMP_SHIFT;
  303. }
  304. /* return details */
  305. *prot_out = prot;
  306. *addr_out = addr;
  307. *log2len = len;
  308. return 0;
  309. }