sun20i-d1.c 6.8 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2022 Samuel Holland <samuel@sholland.org>
  5. */
  6. #include <platform_override.h>
  7. #include <thead_c9xx.h>
  8. #include <sbi/riscv_io.h>
  9. #include <sbi/sbi_bitops.h>
  10. #include <sbi/sbi_ecall_interface.h>
  11. #include <sbi/sbi_error.h>
  12. #include <sbi/sbi_hsm.h>
  13. #include <sbi/sbi_pmu.h>
  14. #include <sbi_utils/fdt/fdt_helper.h>
  15. #include <sbi_utils/irqchip/fdt_irqchip_plic.h>
  16. #define SUN20I_D1_CCU_BASE ((void *)0x02001000)
  17. #define SUN20I_D1_RISCV_CFG_BASE ((void *)0x06010000)
  18. #define SUN20I_D1_PPU_BASE ((void *)0x07001000)
  19. #define SUN20I_D1_PRCM_BASE ((void *)0x07010000)
  20. /*
  21. * CCU
  22. */
  23. #define CCU_BGR_ENABLE (BIT(16) | BIT(0))
  24. #define RISCV_CFG_BGR_REG 0xd0c
  25. #define PPU_BGR_REG 0x1ac
  26. /*
  27. * CSRs
  28. */
  29. #define CSR_MXSTATUS 0x7c0
  30. #define CSR_MHCR 0x7c1
  31. #define CSR_MCOR 0x7c2
  32. #define CSR_MHINT 0x7c5
  33. static unsigned long csr_mxstatus;
  34. static unsigned long csr_mhcr;
  35. static unsigned long csr_mhint;
  36. static void sun20i_d1_csr_save(void)
  37. {
  38. /* Save custom CSRs. */
  39. csr_mxstatus = csr_read(CSR_MXSTATUS);
  40. csr_mhcr = csr_read(CSR_MHCR);
  41. csr_mhint = csr_read(CSR_MHINT);
  42. /* Flush and disable caches. */
  43. csr_write(CSR_MCOR, 0x22);
  44. csr_write(CSR_MHCR, 0x0);
  45. }
  46. static void sun20i_d1_csr_restore(void)
  47. {
  48. /* Invalidate caches and the branch predictor. */
  49. csr_write(CSR_MCOR, 0x70013);
  50. /* Restore custom CSRs, including the cache state. */
  51. csr_write(CSR_MXSTATUS, csr_mxstatus);
  52. csr_write(CSR_MHCR, csr_mhcr);
  53. csr_write(CSR_MHINT, csr_mhint);
  54. }
  55. /*
  56. * PLIC
  57. */
  58. #define PLIC_SOURCES 175
  59. #define PLIC_IE_WORDS (PLIC_SOURCES / 32 + 1)
  60. static u8 plic_priority[1 + PLIC_SOURCES];
  61. static u32 plic_sie[PLIC_IE_WORDS];
  62. static u32 plic_threshold;
  63. static void sun20i_d1_plic_save(void)
  64. {
  65. fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);
  66. fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
  67. }
  68. static void sun20i_d1_plic_restore(void)
  69. {
  70. thead_plic_restore();
  71. fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
  72. fdt_plic_context_restore(true, plic_sie, plic_threshold,
  73. PLIC_IE_WORDS);
  74. }
  75. /*
  76. * PPU
  77. */
  78. #define PPU_PD_ACTIVE_CTRL 0x2c
  79. static void sun20i_d1_ppu_save(void)
  80. {
  81. /* Enable MMIO access. Do not assume S-mode leaves the clock enabled. */
  82. writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_PRCM_BASE + PPU_BGR_REG);
  83. /* Activate automatic power-down during the next WFI. */
  84. writel_relaxed(1, SUN20I_D1_PPU_BASE + PPU_PD_ACTIVE_CTRL);
  85. }
  86. static void sun20i_d1_ppu_restore(void)
  87. {
  88. /* Disable automatic power-down. */
  89. writel_relaxed(0, SUN20I_D1_PPU_BASE + PPU_PD_ACTIVE_CTRL);
  90. }
  91. /*
  92. * RISCV_CFG
  93. */
  94. #define RESET_ENTRY_LO_REG 0x0004
  95. #define RESET_ENTRY_HI_REG 0x0008
  96. #define WAKEUP_EN_REG 0x0020
  97. #define WAKEUP_MASK_REG(i) (0x0024 + 4 * (i))
  98. static void sun20i_d1_riscv_cfg_save(void)
  99. {
  100. /* Enable MMIO access. Do not assume S-mode leaves the clock enabled. */
  101. writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG);
  102. /*
  103. * Copy the SIE bits to the wakeup registers. D1 has 160 "real"
  104. * interrupt sources, numbered 16-175. These are the ones that map to
  105. * the wakeup mask registers (the offset is for GIC compatibility). So
  106. * copying SIE to the wakeup mask needs some bit manipulation.
  107. */
  108. for (int i = 0; i < PLIC_IE_WORDS - 1; i++)
  109. writel_relaxed(plic_sie[i] >> 16 | plic_sie[i + 1] << 16,
  110. SUN20I_D1_RISCV_CFG_BASE + WAKEUP_MASK_REG(i));
  111. /* Enable PPU wakeup for interrupts. */
  112. writel_relaxed(1, SUN20I_D1_RISCV_CFG_BASE + WAKEUP_EN_REG);
  113. }
  114. static void sun20i_d1_riscv_cfg_restore(void)
  115. {
  116. /* Disable PPU wakeup for interrupts. */
  117. writel_relaxed(0, SUN20I_D1_RISCV_CFG_BASE + WAKEUP_EN_REG);
  118. }
  119. static void sun20i_d1_riscv_cfg_init(void)
  120. {
  121. u64 entry = sbi_hartid_to_scratch(0)->warmboot_addr;
  122. /* Enable MMIO access. */
  123. writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG);
  124. /* Program the reset entry address. */
  125. writel_relaxed(entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG);
  126. writel_relaxed(entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG);
  127. }
  128. static int sun20i_d1_hart_suspend(u32 suspend_type)
  129. {
  130. /* Use the generic code for retentive suspend. */
  131. if (!(suspend_type & SBI_HSM_SUSP_NON_RET_BIT))
  132. return SBI_ENOTSUPP;
  133. sun20i_d1_plic_save();
  134. sun20i_d1_ppu_save();
  135. sun20i_d1_riscv_cfg_save();
  136. sun20i_d1_csr_save();
  137. /*
  138. * If no interrupt is pending, this will power down the CPU power
  139. * domain. Otherwise, this will fall through, and the generic HSM
  140. * code will jump to the resume address.
  141. */
  142. wfi();
  143. return 0;
  144. }
  145. static void sun20i_d1_hart_resume(void)
  146. {
  147. sun20i_d1_csr_restore();
  148. sun20i_d1_riscv_cfg_restore();
  149. sun20i_d1_ppu_restore();
  150. sun20i_d1_plic_restore();
  151. }
  152. static const struct sbi_hsm_device sun20i_d1_ppu = {
  153. .name = "sun20i-d1-ppu",
  154. .hart_suspend = sun20i_d1_hart_suspend,
  155. .hart_resume = sun20i_d1_hart_resume,
  156. };
  157. static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
  158. {
  159. if (cold_boot) {
  160. sun20i_d1_riscv_cfg_init();
  161. sbi_hsm_set_device(&sun20i_d1_ppu);
  162. }
  163. return 0;
  164. }
  165. static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
  166. {
  167. unsigned long mip_val;
  168. if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
  169. return;
  170. mip_val = csr_read(CSR_MIP);
  171. /**
  172. * Clear out the OF bit so that next interrupt can be enabled.
  173. * This should be done only when the corresponding overflow interrupt
  174. * bit is cleared. That indicates that software has already handled the
  175. * previous interrupts or the hardware yet to set an overflow interrupt.
  176. * Otherwise, there will be race conditions where we may clear the bit
  177. * the software is yet to handle the interrupt.
  178. */
  179. if (!(mip_val & THEAD_C9XX_MIP_MOIP))
  180. csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
  181. /**
  182. * SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
  183. * while the C9XX has designated enable bits.
  184. * So enable per-counter interrupt on C9xx here.
  185. */
  186. csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
  187. }
  188. static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
  189. {
  190. csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
  191. }
  192. static int thead_c9xx_pmu_irq_bit(void)
  193. {
  194. return THEAD_C9XX_MIP_MOIP;
  195. }
  196. const struct sbi_pmu_device thead_c9xx_pmu_device = {
  197. .hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
  198. .hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
  199. .hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
  200. };
  201. static int sun20i_d1_extensions_init(const struct fdt_match *match,
  202. struct sbi_hart_features *hfeatures)
  203. {
  204. sbi_pmu_set_device(&thead_c9xx_pmu_device);
  205. /* auto-detection doesn't work on t-head c9xx cores */
  206. hfeatures->mhpm_count = 29;
  207. hfeatures->mhpm_bits = 64;
  208. return 0;
  209. }
  210. static const struct fdt_match sun20i_d1_match[] = {
  211. { .compatible = "allwinner,sun20i-d1" },
  212. { },
  213. };
  214. const struct platform_override sun20i_d1 = {
  215. .match_table = sun20i_d1_match,
  216. .final_init = sun20i_d1_final_init,
  217. .extensions_init = sun20i_d1_extensions_init,
  218. };