sbi_emulate_csr.c 4.5 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_encoding.h>
  11. #include <sbi/sbi_bitops.h>
  12. #include <sbi/sbi_console.h>
  13. #include <sbi/sbi_emulate_csr.h>
  14. #include <sbi/sbi_error.h>
  15. #include <sbi/sbi_scratch.h>
  16. #include <sbi/sbi_timer.h>
  17. #include <sbi/sbi_trap.h>
  18. int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
  19. ulong *csr_val)
  20. {
  21. int ret = 0;
  22. ulong cen = -1UL;
  23. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  24. ulong prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
  25. #if __riscv_xlen == 32
  26. bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
  27. #else
  28. bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
  29. #endif
  30. if (prev_mode == PRV_U)
  31. cen = csr_read(CSR_SCOUNTEREN);
  32. switch (csr_num) {
  33. case CSR_HTIMEDELTA:
  34. if (prev_mode == PRV_S && !virt)
  35. *csr_val = sbi_timer_get_delta(scratch);
  36. else
  37. ret = SBI_ENOTSUPP;
  38. break;
  39. case CSR_CYCLE:
  40. if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
  41. return -1;
  42. *csr_val = csr_read(CSR_MCYCLE);
  43. break;
  44. case CSR_TIME:
  45. if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
  46. return -1;
  47. *csr_val = (virt) ? sbi_timer_virt_value(scratch):
  48. sbi_timer_value(scratch);
  49. break;
  50. case CSR_INSTRET:
  51. if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
  52. return -1;
  53. *csr_val = csr_read(CSR_MINSTRET);
  54. break;
  55. case CSR_MHPMCOUNTER3:
  56. if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
  57. return -1;
  58. *csr_val = csr_read(CSR_MHPMCOUNTER3);
  59. break;
  60. case CSR_MHPMCOUNTER4:
  61. if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
  62. return -1;
  63. *csr_val = csr_read(CSR_MHPMCOUNTER4);
  64. break;
  65. #if __riscv_xlen == 32
  66. case CSR_HTIMEDELTAH:
  67. if (prev_mode == PRV_S && !virt)
  68. *csr_val = sbi_timer_get_delta(scratch) >> 32;
  69. else
  70. ret = SBI_ENOTSUPP;
  71. break;
  72. case CSR_CYCLEH:
  73. if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
  74. return -1;
  75. *csr_val = csr_read(CSR_MCYCLEH);
  76. break;
  77. case CSR_TIMEH:
  78. if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
  79. return -1;
  80. *csr_val = (virt) ? sbi_timer_virt_value(scratch) >> 32:
  81. sbi_timer_value(scratch) >> 32;
  82. break;
  83. case CSR_INSTRETH:
  84. if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
  85. return -1;
  86. *csr_val = csr_read(CSR_MINSTRETH);
  87. break;
  88. case CSR_MHPMCOUNTER3H:
  89. if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
  90. return -1;
  91. *csr_val = csr_read(CSR_MHPMCOUNTER3H);
  92. break;
  93. case CSR_MHPMCOUNTER4H:
  94. if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
  95. return -1;
  96. *csr_val = csr_read(CSR_MHPMCOUNTER4H);
  97. break;
  98. #endif
  99. case CSR_MHPMEVENT3:
  100. *csr_val = csr_read(CSR_MHPMEVENT3);
  101. break;
  102. case CSR_MHPMEVENT4:
  103. *csr_val = csr_read(CSR_MHPMEVENT4);
  104. break;
  105. default:
  106. ret = SBI_ENOTSUPP;
  107. break;
  108. };
  109. if (ret)
  110. sbi_dprintf(scratch, "%s: hartid%d: invalid csr_num=0x%x\n",
  111. __func__, current_hartid(), csr_num);
  112. return ret;
  113. }
  114. int sbi_emulate_csr_write(int csr_num, struct sbi_trap_regs *regs,
  115. ulong csr_val)
  116. {
  117. int ret = 0;
  118. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  119. ulong prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
  120. #if __riscv_xlen == 32
  121. bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
  122. #else
  123. bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
  124. #endif
  125. switch (csr_num) {
  126. case CSR_HTIMEDELTA:
  127. if (prev_mode == PRV_S && !virt)
  128. sbi_timer_set_delta(scratch, csr_val);
  129. else
  130. ret = SBI_ENOTSUPP;
  131. break;
  132. case CSR_CYCLE:
  133. csr_write(CSR_MCYCLE, csr_val);
  134. break;
  135. case CSR_INSTRET:
  136. csr_write(CSR_MINSTRET, csr_val);
  137. break;
  138. case CSR_MHPMCOUNTER3:
  139. csr_write(CSR_MHPMCOUNTER3, csr_val);
  140. break;
  141. case CSR_MHPMCOUNTER4:
  142. csr_write(CSR_MHPMCOUNTER4, csr_val);
  143. break;
  144. #if __riscv_xlen == 32
  145. case CSR_HTIMEDELTAH:
  146. if (prev_mode == PRV_S && !virt)
  147. sbi_timer_set_delta_upper(scratch, csr_val);
  148. else
  149. ret = SBI_ENOTSUPP;
  150. break;
  151. case CSR_CYCLEH:
  152. csr_write(CSR_MCYCLEH, csr_val);
  153. break;
  154. case CSR_INSTRETH:
  155. csr_write(CSR_MINSTRETH, csr_val);
  156. break;
  157. case CSR_MHPMCOUNTER3H:
  158. csr_write(CSR_MHPMCOUNTER3H, csr_val);
  159. break;
  160. case CSR_MHPMCOUNTER4H:
  161. csr_write(CSR_MHPMCOUNTER4H, csr_val);
  162. break;
  163. #endif
  164. case CSR_MHPMEVENT3:
  165. csr_write(CSR_MHPMEVENT3, csr_val);
  166. break;
  167. case CSR_MHPMEVENT4:
  168. csr_write(CSR_MHPMEVENT4, csr_val);
  169. break;
  170. default:
  171. ret = SBI_ENOTSUPP;
  172. break;
  173. };
  174. if (ret)
  175. sbi_dprintf(scratch, "%s: hartid%d: invalid csr_num=0x%x\n",
  176. __func__, current_hartid(), csr_num);
  177. return ret;
  178. }