platform.h 4.2 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Andes Technology Corporation
  5. *
  6. * Authors:
  7. * Zong Li <zong@andestech.com>
  8. * Nylon Chen <nylon7@andestech.com>
  9. */
  10. #ifndef _AE350_PLATFORM_H_
  11. #define _AE350_PLATFORM_H_
  12. #define AE350_L2C_ADDR 0xe0500000
  13. /*Memory and Miscellaneous Registers*/
  14. #define CSR_MILMB 0x7c0
  15. #define CSR_MDLMB 0x7c1
  16. #define CSR_MECC_CDOE 0x7c2
  17. #define CSR_MNVEC 0x7c3
  18. #define CSR_MPFTCTL 0x7c5
  19. #define CSR_MCACHECTL 0x7ca
  20. #define CSR_MCCTLBEGINADDR 0x7cb
  21. #define CSR_MCCTLCOMMAND 0x7cc
  22. #define CSR_MCCTLDATA 0x7cc
  23. #define CSR_SCCTLDATA 0x9cd
  24. #define CSR_UCCTLBEGINADDR 0x80c
  25. #define CSR_MMISCCTL 0x7d0
  26. enum sbi_ext_andes_fid {
  27. SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
  28. SBI_EXT_ANDES_GET_MMISC_CTL_STATUS,
  29. SBI_EXT_ANDES_SET_MCACHE_CTL,
  30. SBI_EXT_ANDES_SET_MMISC_CTL,
  31. SBI_EXT_ANDES_ICACHE_OP,
  32. SBI_EXT_ANDES_DCACHE_OP,
  33. SBI_EXT_ANDES_L1CACHE_I_PREFETCH,
  34. SBI_EXT_ANDES_L1CACHE_D_PREFETCH,
  35. SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE,
  36. SBI_EXT_ANDES_WRITE_AROUND,
  37. };
  38. /* nds v5 mmisc_ctl register*/
  39. #define V5_MMISC_CTL_VEC_PLIC_OFFSET 1
  40. #define V5_MMISC_CTL_RVCOMPM_OFFSET 2
  41. #define V5_MMISC_CTL_BRPE_OFFSET 3
  42. #define V5_MMISC_CTL_MSA_OR_UNA_OFFSET 6
  43. #define V5_MMISC_CTL_NON_BLOCKING_OFFSET 8
  44. #define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET 9
  45. #define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET 10
  46. #define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1 13
  47. #define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2 14
  48. #define V5_MMISC_CTL_VEC_PLIC_EN (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
  49. #define V5_MMISC_CTL_RVCOMPM_EN (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
  50. #define V5_MMISC_CTL_BRPE_EN (1UL << V5_MMISC_CTL_BRPE_OFFSET)
  51. #define V5_MMISC_CTL_MSA_OR_UNA_EN (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
  52. #define V5_MMISC_CTL_NON_BLOCKING_EN (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
  53. #define V5_MCACHE_CTL_L1I_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
  54. #define V5_MCACHE_CTL_L1D_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
  55. #define V5_MCACHE_CTL_DC_WAROUND_1_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
  56. #define V5_MCACHE_CTL_DC_WAROUND_2_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
  57. #define V5_MMISC_CTL_MASK (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \
  58. | V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN)
  59. /* nds mcache_ctl register*/
  60. #define V5_MCACHE_CTL_IC_EN_OFFSET 0
  61. #define V5_MCACHE_CTL_DC_EN_OFFSET 1
  62. #define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2
  63. #define V5_MCACHE_CTL_DC_ECCEN_OFFSET 4
  64. #define V5_MCACHE_CTL_IC_RWECC_OFFSET 6
  65. #define V5_MCACHE_CTL_DC_RWECC_OFFSET 7
  66. #define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
  67. /*nds cctl command*/
  68. #define V5_UCCTL_L1D_WBINVAL_ALL 6
  69. #define V5_UCCTL_L1D_WB_ALL 7
  70. #define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
  71. #define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
  72. #define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
  73. #define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
  74. #define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
  75. #define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \
  76. | V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \
  77. | V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \
  78. | V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \
  79. | V5_MCACHE_CTL_DC_WAROUND_2_EN)
  80. #define V5_L2C_CTL_OFFSET 0x8
  81. #define V5_L2C_CTL_ENABLE_OFFSET 0
  82. #define V5_L2C_CTL_IPFDPT_OFFSET 3
  83. #define V5_L2C_CTL_DPFDPT_OFFSET 5
  84. #define V5_L2C_CTL_TRAMOCTL_OFFSET 8
  85. #define V5_L2C_CTL_TRAMICTL_OFFSET 10
  86. #define V5_L2C_CTL_DRAMOCTL_OFFSET 11
  87. #define V5_L2C_CTL_DRAMICTL_OFFSET 13
  88. #define V5_L2C_CTL_ENABLE_MASK (1UL << V5_L2C_CTL_ENABLE_OFFSET)
  89. #define V5_L2C_CTL_IPFDPT_MASK (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
  90. #define V5_L2C_CTL_DPFDPT_MASK (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
  91. #define V5_L2C_CTL_TRAMOCTL_MASK (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
  92. #define V5_L2C_CTL_TRAMICTL_MASK (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
  93. #define V5_L2C_CTL_DRAMOCTL_MASK (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
  94. #define V5_L2C_CTL_DRAMICTL_MASK (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
  95. #endif /* _AE350_PLATFORM_H_ */