platform.c 4.0 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Andes Technology Corporation
  5. *
  6. * Authors:
  7. * Zong Li <zong@andestech.com>
  8. * Nylon Chen <nylon7@andestech.com>
  9. * Yu Chien Peter Lin <peterlin@andestech.com>
  10. */
  11. #include <libfdt.h>
  12. #include <sbi/riscv_asm.h>
  13. #include <sbi/riscv_encoding.h>
  14. #include <sbi/sbi_console.h>
  15. #include <sbi/sbi_const.h>
  16. #include <sbi/sbi_hartmask.h>
  17. #include <sbi/sbi_ipi.h>
  18. #include <sbi/sbi_platform.h>
  19. #include <sbi/sbi_string.h>
  20. #include <sbi/sbi_trap.h>
  21. #include <sbi_utils/fdt/fdt_domain.h>
  22. #include <sbi_utils/fdt/fdt_fixup.h>
  23. #include <sbi_utils/fdt/fdt_helper.h>
  24. #include <sbi_utils/ipi/fdt_ipi.h>
  25. #include <sbi_utils/irqchip/fdt_irqchip.h>
  26. #include <sbi_utils/reset/fdt_reset.h>
  27. #include <sbi_utils/serial/fdt_serial.h>
  28. #include <sbi_utils/timer/fdt_timer.h>
  29. #include "platform.h"
  30. #include "cache.h"
  31. struct sbi_platform platform;
  32. unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
  33. unsigned long arg2, unsigned long arg3,
  34. unsigned long arg4)
  35. {
  36. const char *model;
  37. void *fdt = (void *)arg1;
  38. u32 hartid, hart_count = 0;
  39. int rc, root_offset, cpus_offset, cpu_offset, len;
  40. root_offset = fdt_path_offset(fdt, "/");
  41. if (root_offset < 0)
  42. goto fail;
  43. model = fdt_getprop(fdt, root_offset, "model", &len);
  44. if (model)
  45. sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
  46. cpus_offset = fdt_path_offset(fdt, "/cpus");
  47. if (cpus_offset < 0)
  48. goto fail;
  49. fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
  50. rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
  51. if (rc)
  52. continue;
  53. if (SBI_HARTMASK_MAX_BITS <= hartid)
  54. continue;
  55. hart_count++;
  56. }
  57. platform.hart_count = hart_count;
  58. /* Return original FDT pointer */
  59. return arg1;
  60. fail:
  61. while (1)
  62. wfi();
  63. }
  64. /* Platform final initialization. */
  65. static int ae350_final_init(bool cold_boot)
  66. {
  67. void *fdt;
  68. if (!cold_boot)
  69. return 0;
  70. fdt_reset_init();
  71. fdt = fdt_get_address();
  72. fdt_fixups(fdt);
  73. fdt_domain_fixup(fdt);
  74. return 0;
  75. }
  76. /* Vendor-Specific SBI handler */
  77. static int ae350_vendor_ext_provider(long extid, long funcid,
  78. const struct sbi_trap_regs *regs, unsigned long *out_value,
  79. struct sbi_trap_info *out_trap)
  80. {
  81. int ret = 0;
  82. switch (funcid) {
  83. case SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS:
  84. *out_value = csr_read(CSR_MCACHECTL);
  85. break;
  86. case SBI_EXT_ANDES_GET_MMISC_CTL_STATUS:
  87. *out_value = csr_read(CSR_MMISCCTL);
  88. break;
  89. case SBI_EXT_ANDES_SET_MCACHE_CTL:
  90. ret = mcall_set_mcache_ctl(regs->a0);
  91. break;
  92. case SBI_EXT_ANDES_SET_MMISC_CTL:
  93. ret = mcall_set_mmisc_ctl(regs->a0);
  94. break;
  95. case SBI_EXT_ANDES_ICACHE_OP:
  96. ret = mcall_icache_op(regs->a0);
  97. break;
  98. case SBI_EXT_ANDES_DCACHE_OP:
  99. ret = mcall_dcache_op(regs->a0);
  100. break;
  101. case SBI_EXT_ANDES_L1CACHE_I_PREFETCH:
  102. ret = mcall_l1_cache_i_prefetch_op(regs->a0);
  103. break;
  104. case SBI_EXT_ANDES_L1CACHE_D_PREFETCH:
  105. ret = mcall_l1_cache_d_prefetch_op(regs->a0);
  106. break;
  107. case SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE:
  108. ret = mcall_non_blocking_load_store(regs->a0);
  109. break;
  110. case SBI_EXT_ANDES_WRITE_AROUND:
  111. ret = mcall_write_around(regs->a0);
  112. break;
  113. default:
  114. sbi_printf("Unsupported vendor sbi call : %ld\n", funcid);
  115. asm volatile("ebreak");
  116. }
  117. return ret;
  118. }
  119. static int ae350_domains_init(void)
  120. {
  121. return fdt_domains_populate(fdt_get_address());
  122. }
  123. /* Platform descriptor. */
  124. const struct sbi_platform_operations platform_ops = {
  125. .final_init = ae350_final_init,
  126. .domains_init = ae350_domains_init,
  127. .console_init = fdt_serial_init,
  128. .irqchip_init = fdt_irqchip_init,
  129. .ipi_init = fdt_ipi_init,
  130. .timer_init = fdt_timer_init,
  131. .vendor_ext_provider = ae350_vendor_ext_provider
  132. };
  133. struct sbi_platform platform = {
  134. .opensbi_version = OPENSBI_VERSION,
  135. .platform_version =
  136. SBI_PLATFORM_VERSION(CONFIG_PLATFORM_ANDES_AE350_MAJOR_VER,
  137. CONFIG_PLATFORM_ANDES_AE350_MINOR_VER),
  138. .name = CONFIG_PLATFORM_ANDES_AE350_NAME,
  139. .features = SBI_PLATFORM_DEFAULT_FEATURES,
  140. .hart_count = SBI_HARTMASK_MAX_BITS,
  141. .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
  142. .platform_ops_addr = (unsigned long)&platform_ops
  143. };