sbi_ecall_interface.h 8.6 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #ifndef __SBI_ECALL_INTERFACE_H__
  10. #define __SBI_ECALL_INTERFACE_H__
  11. /* clang-format off */
  12. /* SBI Extension IDs */
  13. #define SBI_EXT_0_1_SET_TIMER 0x0
  14. #define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
  15. #define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
  16. #define SBI_EXT_0_1_CLEAR_IPI 0x3
  17. #define SBI_EXT_0_1_SEND_IPI 0x4
  18. #define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
  19. #define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
  20. #define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
  21. #define SBI_EXT_0_1_SHUTDOWN 0x8
  22. #define SBI_EXT_BASE 0x10
  23. #define SBI_EXT_TIME 0x54494D45
  24. #define SBI_EXT_IPI 0x735049
  25. #define SBI_EXT_RFENCE 0x52464E43
  26. #define SBI_EXT_HSM 0x48534D
  27. #define SBI_EXT_SRST 0x53525354
  28. #define SBI_EXT_PMU 0x504D55
  29. #define SBI_EXT_DBCN 0x4442434E
  30. #define SBI_EXT_SUSP 0x53555350
  31. /* SBI function IDs for BASE extension*/
  32. #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
  33. #define SBI_EXT_BASE_GET_IMP_ID 0x1
  34. #define SBI_EXT_BASE_GET_IMP_VERSION 0x2
  35. #define SBI_EXT_BASE_PROBE_EXT 0x3
  36. #define SBI_EXT_BASE_GET_MVENDORID 0x4
  37. #define SBI_EXT_BASE_GET_MARCHID 0x5
  38. #define SBI_EXT_BASE_GET_MIMPID 0x6
  39. /* SBI function IDs for TIME extension*/
  40. #define SBI_EXT_TIME_SET_TIMER 0x0
  41. /* SBI function IDs for IPI extension*/
  42. #define SBI_EXT_IPI_SEND_IPI 0x0
  43. #define SBI_EXT_IPI_SEND_EXT_DOMAIN 0x1
  44. #define SBI_EXT_IPI_SET_AMP_DATA_ADDR 0x2
  45. /* SBI function IDs for RFENCE extension*/
  46. #define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
  47. #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1
  48. #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2
  49. #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x3
  50. #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x4
  51. #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x5
  52. #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x6
  53. /* SBI function IDs for HSM extension */
  54. #define SBI_EXT_HSM_HART_START 0x0
  55. #define SBI_EXT_HSM_HART_STOP 0x1
  56. #define SBI_EXT_HSM_HART_GET_STATUS 0x2
  57. #define SBI_EXT_HSM_HART_SUSPEND 0x3
  58. #define SBI_HSM_STATE_STARTED 0x0
  59. #define SBI_HSM_STATE_STOPPED 0x1
  60. #define SBI_HSM_STATE_START_PENDING 0x2
  61. #define SBI_HSM_STATE_STOP_PENDING 0x3
  62. #define SBI_HSM_STATE_SUSPENDED 0x4
  63. #define SBI_HSM_STATE_SUSPEND_PENDING 0x5
  64. #define SBI_HSM_STATE_RESUME_PENDING 0x6
  65. #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
  66. #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
  67. #define SBI_HSM_SUSP_PLAT_BASE 0x10000000
  68. #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
  69. #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
  70. #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
  71. #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
  72. #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
  73. SBI_HSM_SUSP_PLAT_BASE)
  74. #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
  75. SBI_HSM_SUSP_BASE_MASK)
  76. /* SBI function IDs for SRST extension */
  77. #define SBI_EXT_SRST_RESET 0x0
  78. #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
  79. #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
  80. #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
  81. #define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT
  82. #define SBI_SRST_RESET_REASON_NONE 0x0
  83. #define SBI_SRST_RESET_REASON_SYSFAIL 0x1
  84. /* SBI function IDs for PMU extension */
  85. #define SBI_EXT_PMU_NUM_COUNTERS 0x0
  86. #define SBI_EXT_PMU_COUNTER_GET_INFO 0x1
  87. #define SBI_EXT_PMU_COUNTER_CFG_MATCH 0x2
  88. #define SBI_EXT_PMU_COUNTER_START 0x3
  89. #define SBI_EXT_PMU_COUNTER_STOP 0x4
  90. #define SBI_EXT_PMU_COUNTER_FW_READ 0x5
  91. #define SBI_EXT_PMU_COUNTER_FW_READ_HI 0x6
  92. /** General pmu event codes specified in SBI PMU extension */
  93. enum sbi_pmu_hw_generic_events_t {
  94. SBI_PMU_HW_NO_EVENT = 0,
  95. SBI_PMU_HW_CPU_CYCLES = 1,
  96. SBI_PMU_HW_INSTRUCTIONS = 2,
  97. SBI_PMU_HW_CACHE_REFERENCES = 3,
  98. SBI_PMU_HW_CACHE_MISSES = 4,
  99. SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
  100. SBI_PMU_HW_BRANCH_MISSES = 6,
  101. SBI_PMU_HW_BUS_CYCLES = 7,
  102. SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
  103. SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
  104. SBI_PMU_HW_REF_CPU_CYCLES = 10,
  105. SBI_PMU_HW_GENERAL_MAX,
  106. };
  107. /**
  108. * Generalized hardware cache events:
  109. *
  110. * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
  111. * { read, write, prefetch } x
  112. * { accesses, misses }
  113. */
  114. enum sbi_pmu_hw_cache_id {
  115. SBI_PMU_HW_CACHE_L1D = 0,
  116. SBI_PMU_HW_CACHE_L1I = 1,
  117. SBI_PMU_HW_CACHE_LL = 2,
  118. SBI_PMU_HW_CACHE_DTLB = 3,
  119. SBI_PMU_HW_CACHE_ITLB = 4,
  120. SBI_PMU_HW_CACHE_BPU = 5,
  121. SBI_PMU_HW_CACHE_NODE = 6,
  122. SBI_PMU_HW_CACHE_MAX,
  123. };
  124. enum sbi_pmu_hw_cache_op_id {
  125. SBI_PMU_HW_CACHE_OP_READ = 0,
  126. SBI_PMU_HW_CACHE_OP_WRITE = 1,
  127. SBI_PMU_HW_CACHE_OP_PREFETCH = 2,
  128. SBI_PMU_HW_CACHE_OP_MAX,
  129. };
  130. enum sbi_pmu_hw_cache_op_result_id {
  131. SBI_PMU_HW_CACHE_RESULT_ACCESS = 0,
  132. SBI_PMU_HW_CACHE_RESULT_MISS = 1,
  133. SBI_PMU_HW_CACHE_RESULT_MAX,
  134. };
  135. /**
  136. * Special "firmware" events provided by the OpenSBI, even if the hardware
  137. * does not support performance events. These events are encoded as a raw
  138. * event type in Linux kernel perf framework.
  139. */
  140. enum sbi_pmu_fw_event_code_id {
  141. SBI_PMU_FW_MISALIGNED_LOAD = 0,
  142. SBI_PMU_FW_MISALIGNED_STORE = 1,
  143. SBI_PMU_FW_ACCESS_LOAD = 2,
  144. SBI_PMU_FW_ACCESS_STORE = 3,
  145. SBI_PMU_FW_ILLEGAL_INSN = 4,
  146. SBI_PMU_FW_SET_TIMER = 5,
  147. SBI_PMU_FW_IPI_SENT = 6,
  148. SBI_PMU_FW_IPI_RECVD = 7,
  149. SBI_PMU_FW_FENCE_I_SENT = 8,
  150. SBI_PMU_FW_FENCE_I_RECVD = 9,
  151. SBI_PMU_FW_SFENCE_VMA_SENT = 10,
  152. SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
  153. SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
  154. SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
  155. SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
  156. SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
  157. SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
  158. SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
  159. SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
  160. SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
  161. SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
  162. SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
  163. SBI_PMU_FW_MAX,
  164. /*
  165. * Event codes 22 to 255 are reserved for future use.
  166. * Event codes 256 to 65534 are reserved for SBI implementation
  167. * specific custom firmware events.
  168. */
  169. SBI_PMU_FW_RESERVED_MAX = 0xFFFE,
  170. /*
  171. * Event code 0xFFFF is used for platform specific firmware
  172. * events where the event data contains any event specific information.
  173. */
  174. SBI_PMU_FW_PLATFORM = 0xFFFF,
  175. };
  176. /** SBI PMU event idx type */
  177. enum sbi_pmu_event_type_id {
  178. SBI_PMU_EVENT_TYPE_HW = 0x0,
  179. SBI_PMU_EVENT_TYPE_HW_CACHE = 0x1,
  180. SBI_PMU_EVENT_TYPE_HW_RAW = 0x2,
  181. SBI_PMU_EVENT_TYPE_FW = 0xf,
  182. SBI_PMU_EVENT_TYPE_MAX,
  183. };
  184. /** SBI PMU counter type */
  185. enum sbi_pmu_ctr_type {
  186. SBI_PMU_CTR_TYPE_HW = 0,
  187. SBI_PMU_CTR_TYPE_FW,
  188. };
  189. /* Helper macros to decode event idx */
  190. #define SBI_PMU_EVENT_IDX_OFFSET 20
  191. #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
  192. #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
  193. #define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
  194. #define SBI_PMU_EVENT_RAW_IDX 0x20000
  195. #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
  196. #define SBI_PMU_EVENT_HW_CACHE_OPS_RESULT 0x1
  197. #define SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK 0x6
  198. #define SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET 1
  199. #define SBI_PMU_EVENT_HW_CACHE_ID_MASK 0xfff8
  200. #define SBI_PMU_EVENT_HW_CACHE_ID_OFFSET 3
  201. /* Flags defined for config matching function */
  202. #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0)
  203. #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1)
  204. #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2)
  205. #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3)
  206. #define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4)
  207. #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5)
  208. #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6)
  209. #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7)
  210. /* Flags defined for counter start function */
  211. #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
  212. /* Flags defined for counter stop function */
  213. #define SBI_PMU_STOP_FLAG_RESET (1 << 0)
  214. /* SBI function IDs for DBCN extension */
  215. #define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
  216. #define SBI_EXT_DBCN_CONSOLE_READ 0x1
  217. #define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
  218. /* SBI function IDs for SUSP extension */
  219. #define SBI_EXT_SUSP_SUSPEND 0x0
  220. #define SBI_SUSP_SLEEP_TYPE_SUSPEND 0x0
  221. #define SBI_SUSP_SLEEP_TYPE_LAST SBI_SUSP_SLEEP_TYPE_SUSPEND
  222. #define SBI_SUSP_PLATFORM_SLEEP_START 0x80000000
  223. /* SBI base specification related macros */
  224. #define SBI_SPEC_VERSION_MAJOR_OFFSET 24
  225. #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
  226. #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
  227. #define SBI_EXT_VENDOR_START 0x09000000
  228. #define SBI_EXT_VENDOR_END 0x09FFFFFF
  229. #define SBI_EXT_FIRMWARE_START 0x0A000000
  230. #define SBI_EXT_FIRMWARE_END 0x0AFFFFFF
  231. /* SBI return error codes */
  232. #define SBI_SUCCESS 0
  233. #define SBI_ERR_FAILED -1
  234. #define SBI_ERR_NOT_SUPPORTED -2
  235. #define SBI_ERR_INVALID_PARAM -3
  236. #define SBI_ERR_DENIED -4
  237. #define SBI_ERR_INVALID_ADDRESS -5
  238. #define SBI_ERR_ALREADY_AVAILABLE -6
  239. #define SBI_ERR_ALREADY_STARTED -7
  240. #define SBI_ERR_ALREADY_STOPPED -8
  241. #define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED
  242. /* clang-format on */
  243. #endif