sbi_ipi.c 6.1 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. * Nick Kossifidis <mick@ics.forth.gr>
  9. */
  10. #include <sbi/riscv_asm.h>
  11. #include <sbi/riscv_atomic.h>
  12. #include <sbi/riscv_barrier.h>
  13. #include <sbi/sbi_bitops.h>
  14. #include <sbi/sbi_domain.h>
  15. #include <sbi/sbi_error.h>
  16. #include <sbi/sbi_hart.h>
  17. #include <sbi/sbi_hsm.h>
  18. #include <sbi/sbi_init.h>
  19. #include <sbi/sbi_ipi.h>
  20. #include <sbi/sbi_platform.h>
  21. #include <sbi/sbi_pmu.h>
  22. #include <sbi/sbi_string.h>
  23. #include <sbi/sbi_tlb.h>
  24. struct sbi_ipi_data {
  25. unsigned long ipi_type;
  26. };
  27. static unsigned long ipi_data_off;
  28. static const struct sbi_ipi_device *ipi_dev = NULL;
  29. static const struct sbi_ipi_event_ops *ipi_ops_array[SBI_IPI_EVENT_MAX];
  30. static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
  31. u32 event, void *data)
  32. {
  33. int ret;
  34. struct sbi_scratch *remote_scratch = NULL;
  35. struct sbi_ipi_data *ipi_data;
  36. const struct sbi_ipi_event_ops *ipi_ops;
  37. if ((SBI_IPI_EVENT_MAX <= event) ||
  38. !ipi_ops_array[event])
  39. return SBI_EINVAL;
  40. ipi_ops = ipi_ops_array[event];
  41. remote_scratch = sbi_hartid_to_scratch(remote_hartid);
  42. if (!remote_scratch)
  43. return SBI_EINVAL;
  44. ipi_data = sbi_scratch_offset_ptr(remote_scratch, ipi_data_off);
  45. if (ipi_ops->update) {
  46. ret = ipi_ops->update(scratch, remote_scratch,
  47. remote_hartid, data);
  48. if (ret < 0)
  49. return ret;
  50. }
  51. /*
  52. * Set IPI type on remote hart's scratch area and
  53. * trigger the interrupt
  54. */
  55. atomic_raw_set_bit(event, &ipi_data->ipi_type);
  56. smp_wmb();
  57. if (ipi_dev && ipi_dev->ipi_send)
  58. ipi_dev->ipi_send(remote_hartid);
  59. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_IPI_SENT);
  60. if (ipi_ops->sync)
  61. ipi_ops->sync(scratch);
  62. return 0;
  63. }
  64. /**
  65. * As this this function only handlers scalar values of hart mask, it must be
  66. * set to all online harts if the intention is to send IPIs to all the harts.
  67. * If hmask is zero, no IPIs will be sent.
  68. */
  69. int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data)
  70. {
  71. int rc;
  72. ulong i, m;
  73. struct sbi_domain *dom = sbi_domain_thishart_ptr();
  74. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  75. if (hbase != -1UL) {
  76. rc = sbi_hsm_hart_interruptible_mask(dom, hbase, &m);
  77. if (rc)
  78. return rc;
  79. m &= hmask;
  80. /* Send IPIs */
  81. for (i = hbase; m; i++, m >>= 1) {
  82. if (m & 1UL)
  83. sbi_ipi_send(scratch, i, event, data);
  84. }
  85. } else {
  86. hbase = 0;
  87. while (!sbi_hsm_hart_interruptible_mask(dom, hbase, &m)) {
  88. /* Send IPIs */
  89. for (i = hbase; m; i++, m >>= 1) {
  90. if (m & 1UL)
  91. sbi_ipi_send(scratch, i, event, data);
  92. }
  93. hbase += BITS_PER_LONG;
  94. }
  95. }
  96. return 0;
  97. }
  98. int sbi_ipi_event_create(const struct sbi_ipi_event_ops *ops)
  99. {
  100. int i, ret = SBI_ENOSPC;
  101. if (!ops || !ops->process)
  102. return SBI_EINVAL;
  103. for (i = 0; i < SBI_IPI_EVENT_MAX; i++) {
  104. if (!ipi_ops_array[i]) {
  105. ret = i;
  106. ipi_ops_array[i] = ops;
  107. break;
  108. }
  109. }
  110. return ret;
  111. }
  112. void sbi_ipi_event_destroy(u32 event)
  113. {
  114. if (SBI_IPI_EVENT_MAX <= event)
  115. return;
  116. ipi_ops_array[event] = NULL;
  117. }
  118. static void sbi_ipi_process_smode(struct sbi_scratch *scratch)
  119. {
  120. csr_set(CSR_MIP, MIP_SSIP);
  121. }
  122. static struct sbi_ipi_event_ops ipi_smode_ops = {
  123. .name = "IPI_SMODE",
  124. .process = sbi_ipi_process_smode,
  125. };
  126. static u32 ipi_smode_event = SBI_IPI_EVENT_MAX;
  127. int sbi_ipi_send_smode(ulong hmask, ulong hbase)
  128. {
  129. return sbi_ipi_send_many(hmask, hbase, ipi_smode_event, NULL);
  130. }
  131. void sbi_ipi_clear_smode(void)
  132. {
  133. csr_clear(CSR_MIP, MIP_SSIP);
  134. }
  135. static void sbi_ipi_process_halt(struct sbi_scratch *scratch)
  136. {
  137. sbi_hsm_hart_stop(scratch, true);
  138. }
  139. static struct sbi_ipi_event_ops ipi_halt_ops = {
  140. .name = "IPI_HALT",
  141. .process = sbi_ipi_process_halt,
  142. };
  143. static u32 ipi_halt_event = SBI_IPI_EVENT_MAX;
  144. int sbi_ipi_send_halt(ulong hmask, ulong hbase)
  145. {
  146. return sbi_ipi_send_many(hmask, hbase, ipi_halt_event, NULL);
  147. }
  148. void sbi_ipi_process(void)
  149. {
  150. unsigned long ipi_type;
  151. unsigned int ipi_event;
  152. const struct sbi_ipi_event_ops *ipi_ops;
  153. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  154. struct sbi_ipi_data *ipi_data =
  155. sbi_scratch_offset_ptr(scratch, ipi_data_off);
  156. u32 hartid = current_hartid();
  157. sbi_pmu_ctr_incr_fw(SBI_PMU_FW_IPI_RECVD);
  158. if (ipi_dev && ipi_dev->ipi_clear)
  159. ipi_dev->ipi_clear(hartid);
  160. ipi_type = atomic_raw_xchg_ulong(&ipi_data->ipi_type, 0);
  161. ipi_event = 0;
  162. while (ipi_type) {
  163. if (!(ipi_type & 1UL))
  164. goto skip;
  165. ipi_ops = ipi_ops_array[ipi_event];
  166. if (ipi_ops && ipi_ops->process)
  167. ipi_ops->process(scratch);
  168. skip:
  169. ipi_type = ipi_type >> 1;
  170. ipi_event++;
  171. };
  172. }
  173. int sbi_ipi_raw_send(u32 target_hart)
  174. {
  175. if (!ipi_dev || !ipi_dev->ipi_send)
  176. return SBI_EINVAL;
  177. ipi_dev->ipi_send(target_hart);
  178. return 0;
  179. }
  180. void sbi_ipi_raw_clear(u32 target_hart)
  181. {
  182. if (ipi_dev && ipi_dev->ipi_clear)
  183. ipi_dev->ipi_clear(target_hart);
  184. }
  185. const struct sbi_ipi_device *sbi_ipi_get_device(void)
  186. {
  187. return ipi_dev;
  188. }
  189. void sbi_ipi_set_device(const struct sbi_ipi_device *dev)
  190. {
  191. if (!dev || ipi_dev)
  192. return;
  193. ipi_dev = dev;
  194. }
  195. int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot)
  196. {
  197. int ret;
  198. struct sbi_ipi_data *ipi_data;
  199. if (cold_boot) {
  200. ipi_data_off = sbi_scratch_alloc_offset(sizeof(*ipi_data));
  201. if (!ipi_data_off)
  202. return SBI_ENOMEM;
  203. ret = sbi_ipi_event_create(&ipi_smode_ops);
  204. if (ret < 0)
  205. return ret;
  206. ipi_smode_event = ret;
  207. ret = sbi_ipi_event_create(&ipi_halt_ops);
  208. if (ret < 0)
  209. return ret;
  210. ipi_halt_event = ret;
  211. } else {
  212. if (!ipi_data_off)
  213. return SBI_ENOMEM;
  214. if (SBI_IPI_EVENT_MAX <= ipi_smode_event ||
  215. SBI_IPI_EVENT_MAX <= ipi_halt_event)
  216. return SBI_ENOSPC;
  217. }
  218. ipi_data = sbi_scratch_offset_ptr(scratch, ipi_data_off);
  219. ipi_data->ipi_type = 0x00;
  220. /*
  221. * Initialize platform IPI support. This will also clear any
  222. * pending IPIs for current/calling HART.
  223. */
  224. ret = sbi_platform_ipi_init(sbi_platform_ptr(scratch), cold_boot);
  225. if (ret)
  226. return ret;
  227. /* Enable software interrupts */
  228. csr_set(CSR_MIE, MIP_MSIP);
  229. return 0;
  230. }
  231. void sbi_ipi_exit(struct sbi_scratch *scratch)
  232. {
  233. /* Disable software interrupts */
  234. csr_clear(CSR_MIE, MIP_MSIP);
  235. /* Process pending IPIs */
  236. sbi_ipi_process();
  237. /* Platform exit */
  238. sbi_platform_ipi_exit(sbi_platform_ptr(scratch));
  239. }