sbi_pmu.h 4.1 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #ifndef __SBI_PMU_H__
  10. #define __SBI_PMU_H__
  11. #include <sbi/sbi_types.h>
  12. struct sbi_scratch;
  13. /* Event related macros */
  14. /* Maximum number of hardware events that can mapped by OpenSBI */
  15. #define SBI_PMU_HW_EVENT_MAX 256
  16. /* Counter related macros */
  17. #define SBI_PMU_FW_CTR_MAX 16
  18. #define SBI_PMU_HW_CTR_MAX 32
  19. #define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX)
  20. #define SBI_PMU_FIXED_CTR_MASK 0x07
  21. struct sbi_pmu_device {
  22. /** Name of the PMU platform device */
  23. char name[32];
  24. /**
  25. * Validate event code of custom firmware event
  26. */
  27. int (*fw_event_validate_encoding)(uint32_t hartid, uint64_t event_data);
  28. /**
  29. * Match custom firmware counter with custom firmware event
  30. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  31. */
  32. bool (*fw_counter_match_encoding)(uint32_t hartid,
  33. uint32_t counter_index,
  34. uint64_t event_data);
  35. /**
  36. * Fetch the max width of this counter in number of bits.
  37. */
  38. int (*fw_counter_width)(void);
  39. /**
  40. * Read value of custom firmware counter
  41. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  42. */
  43. uint64_t (*fw_counter_read_value)(uint32_t hartid,
  44. uint32_t counter_index);
  45. /**
  46. * Write value to custom firmware counter
  47. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  48. */
  49. void (*fw_counter_write_value)(uint32_t hartid, uint32_t counter_index,
  50. uint64_t value);
  51. /**
  52. * Start custom firmware counter
  53. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  54. */
  55. int (*fw_counter_start)(uint32_t hartid, uint32_t counter_index,
  56. uint64_t event_data);
  57. /**
  58. * Stop custom firmware counter
  59. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  60. */
  61. int (*fw_counter_stop)(uint32_t hartid, uint32_t counter_index);
  62. /**
  63. * Custom enable irq for hardware counter
  64. * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
  65. */
  66. void (*hw_counter_enable_irq)(uint32_t counter_index);
  67. /**
  68. * Custom disable irq for hardware counter
  69. * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
  70. */
  71. void (*hw_counter_disable_irq)(uint32_t counter_index);
  72. /**
  73. * Custom function returning the machine-specific irq-bit.
  74. */
  75. int (*hw_counter_irq_bit)(void);
  76. };
  77. /** Get the PMU platform device */
  78. const struct sbi_pmu_device *sbi_pmu_get_device(void);
  79. /** Set the PMU platform device */
  80. void sbi_pmu_set_device(const struct sbi_pmu_device *dev);
  81. /** Initialize PMU */
  82. int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
  83. /** Reset PMU during hart exit */
  84. void sbi_pmu_exit(struct sbi_scratch *scratch);
  85. /** Return the pmu irq bit depending on extension existence */
  86. int sbi_pmu_irq_bit(void);
  87. /**
  88. * Add the hardware event to counter mapping information. This should be called
  89. * from the platform code to update the mapping table.
  90. * @param eidx_start Start of the event idx range for supported counters
  91. * @param eidx_end End of the event idx range for supported counters
  92. * @param cmap A bitmap representing counters supporting the event range
  93. * @return 0 on success, error otherwise.
  94. */
  95. int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap);
  96. /**
  97. * Add the raw hardware event selector and supported counter information. This
  98. * should be called from the platform code to update the mapping table.
  99. * @param info a pointer to the hardware event info
  100. * @return 0 on success, error otherwise.
  101. */
  102. int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap);
  103. int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval);
  104. int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask,
  105. unsigned long flag);
  106. int sbi_pmu_ctr_start(unsigned long cidx_base, unsigned long cidx_mask,
  107. unsigned long flags, uint64_t ival);
  108. int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info);
  109. unsigned long sbi_pmu_num_ctr(void);
  110. int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
  111. unsigned long flags, unsigned long event_idx,
  112. uint64_t event_data);
  113. int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id);
  114. #endif