sbi_init.c 10 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_atomic.h>
  11. #include <sbi/riscv_barrier.h>
  12. #include <sbi/riscv_locks.h>
  13. #include <sbi/sbi_console.h>
  14. #include <sbi/sbi_domain.h>
  15. #include <sbi/sbi_ecall.h>
  16. #include <sbi/sbi_hart.h>
  17. #include <sbi/sbi_hartmask.h>
  18. #include <sbi/sbi_hsm.h>
  19. #include <sbi/sbi_ipi.h>
  20. #include <sbi/sbi_platform.h>
  21. #include <sbi/sbi_system.h>
  22. #include <sbi/sbi_string.h>
  23. #include <sbi/sbi_timer.h>
  24. #include <sbi/sbi_tlb.h>
  25. #include <sbi/sbi_version.h>
  26. #define BANNER \
  27. " ____ _____ ____ _____\n" \
  28. " / __ \\ / ____| _ \\_ _|\n" \
  29. " | | | |_ __ ___ _ __ | (___ | |_) || |\n" \
  30. " | | | | '_ \\ / _ \\ '_ \\ \\___ \\| _ < | |\n" \
  31. " | |__| | |_) | __/ | | |____) | |_) || |_\n" \
  32. " \\____/| .__/ \\___|_| |_|_____/|____/_____|\n" \
  33. " | |\n" \
  34. " |_|\n\n"
  35. static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
  36. {
  37. int xlen;
  38. char str[128];
  39. const struct sbi_domain *dom = sbi_domain_thishart_ptr();
  40. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  41. #ifdef OPENSBI_VERSION_GIT
  42. sbi_printf("\nOpenSBI %s\n", OPENSBI_VERSION_GIT);
  43. #else
  44. sbi_printf("\nOpenSBI v%d.%d\n", OPENSBI_VERSION_MAJOR,
  45. OPENSBI_VERSION_MINOR);
  46. #endif
  47. sbi_printf(BANNER);
  48. /* Determine MISA XLEN and MISA string */
  49. xlen = misa_xlen();
  50. if (xlen < 1) {
  51. sbi_printf("Error %d getting MISA XLEN\n", xlen);
  52. sbi_hart_hang();
  53. }
  54. /* Platform details */
  55. sbi_printf("Platform Name : %s\n", sbi_platform_name(plat));
  56. sbi_platform_get_features_str(plat, str, sizeof(str));
  57. sbi_printf("Platform Features : %s\n", str);
  58. sbi_printf("Platform HART Count : %u\n",
  59. sbi_platform_hart_count(plat));
  60. /* Firmware details */
  61. sbi_printf("Firmware Base : 0x%lx\n", scratch->fw_start);
  62. sbi_printf("Firmware Size : %d KB\n",
  63. (u32)(scratch->fw_size / 1024));
  64. /* SBI details */
  65. sbi_printf("Runtime SBI Version : %d.%d\n",
  66. sbi_ecall_version_major(), sbi_ecall_version_minor());
  67. sbi_printf("\n");
  68. /* Domain details */
  69. sbi_domain_dump_all("");
  70. /* Boot HART details */
  71. sbi_printf("Boot HART ID : %u\n", hartid);
  72. sbi_printf("Boot HART Domain : %s\n", dom->name);
  73. misa_string(xlen, str, sizeof(str));
  74. sbi_printf("Boot HART ISA : %s\n", str);
  75. sbi_hart_get_features_str(scratch, str, sizeof(str));
  76. sbi_printf("Boot HART Features : %s\n", str);
  77. sbi_printf("Boot HART PMP Count : %d\n", sbi_hart_pmp_count(scratch));
  78. sbi_printf("Boot HART MHPM Count: %d\n", sbi_hart_mhpm_count(scratch));
  79. sbi_hart_delegation_dump(scratch, "Boot HART ", " ");
  80. }
  81. static spinlock_t coldboot_lock = SPIN_LOCK_INITIALIZER;
  82. static struct sbi_hartmask coldboot_wait_hmask = { 0 };
  83. static unsigned long coldboot_done;
  84. static void wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
  85. {
  86. unsigned long saved_mie, cmip;
  87. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  88. /* Save MIE CSR */
  89. saved_mie = csr_read(CSR_MIE);
  90. /* Set MSIE bit to receive IPI */
  91. csr_set(CSR_MIE, MIP_MSIP);
  92. /* Acquire coldboot lock */
  93. spin_lock(&coldboot_lock);
  94. /* Mark current HART as waiting */
  95. sbi_hartmask_set_hart(hartid, &coldboot_wait_hmask);
  96. /* Release coldboot lock */
  97. spin_unlock(&coldboot_lock);
  98. /* Wait for coldboot to finish using WFI */
  99. while (!__smp_load_acquire(&coldboot_done)) {
  100. do {
  101. wfi();
  102. cmip = csr_read(CSR_MIP);
  103. } while (!(cmip & MIP_MSIP));
  104. };
  105. /* Acquire coldboot lock */
  106. spin_lock(&coldboot_lock);
  107. /* Unmark current HART as waiting */
  108. sbi_hartmask_clear_hart(hartid, &coldboot_wait_hmask);
  109. /* Release coldboot lock */
  110. spin_unlock(&coldboot_lock);
  111. /* Restore MIE CSR */
  112. csr_write(CSR_MIE, saved_mie);
  113. /* Clear current HART IPI */
  114. sbi_platform_ipi_clear(plat, hartid);
  115. }
  116. static void wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
  117. {
  118. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  119. /* Mark coldboot done */
  120. __smp_store_release(&coldboot_done, 1);
  121. /* Acquire coldboot lock */
  122. spin_lock(&coldboot_lock);
  123. /* Send an IPI to all HARTs waiting for coldboot */
  124. for (int i = 0; i <= sbi_scratch_last_hartid(); i++) {
  125. if ((i != hartid) &&
  126. sbi_hartmask_test_hart(i, &coldboot_wait_hmask))
  127. sbi_platform_ipi_send(plat, i);
  128. }
  129. /* Release coldboot lock */
  130. spin_unlock(&coldboot_lock);
  131. }
  132. static unsigned long init_count_offset;
  133. static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
  134. {
  135. int rc;
  136. unsigned long *init_count;
  137. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  138. /* Note: This has to be first thing in coldboot init sequence */
  139. rc = sbi_scratch_init(scratch);
  140. if (rc)
  141. sbi_hart_hang();
  142. /* Note: This has to be second thing in coldboot init sequence */
  143. rc = sbi_domain_init(scratch, hartid);
  144. if (rc)
  145. sbi_hart_hang();
  146. init_count_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__,
  147. "INIT_COUNT");
  148. if (!init_count_offset)
  149. sbi_hart_hang();
  150. rc = sbi_hsm_init(scratch, hartid, TRUE);
  151. if (rc)
  152. sbi_hart_hang();
  153. rc = sbi_platform_early_init(plat, TRUE);
  154. if (rc)
  155. sbi_hart_hang();
  156. rc = sbi_hart_init(scratch, TRUE);
  157. if (rc)
  158. sbi_hart_hang();
  159. rc = sbi_console_init(scratch);
  160. if (rc)
  161. sbi_hart_hang();
  162. rc = sbi_platform_irqchip_init(plat, TRUE);
  163. if (rc)
  164. sbi_hart_hang();
  165. rc = sbi_ipi_init(scratch, TRUE);
  166. if (rc)
  167. sbi_hart_hang();
  168. rc = sbi_tlb_init(scratch, TRUE);
  169. if (rc)
  170. sbi_hart_hang();
  171. rc = sbi_timer_init(scratch, TRUE);
  172. if (rc)
  173. sbi_hart_hang();
  174. rc = sbi_ecall_init();
  175. if (rc)
  176. sbi_hart_hang();
  177. /*
  178. * Note: Finalize domains after HSM initialization so that we
  179. * can startup non-root domains.
  180. * Note: Finalize domains before HART PMP configuration so
  181. * that we use correct domain for configuring PMP.
  182. */
  183. rc = sbi_domain_finalize(scratch, hartid);
  184. if (rc)
  185. sbi_hart_hang();
  186. rc = sbi_hart_pmp_configure(scratch);
  187. if (rc)
  188. sbi_hart_hang();
  189. /*
  190. * Note: Platform final initialization should be last so that
  191. * it sees correct domain assignment and PMP configuration.
  192. */
  193. rc = sbi_platform_final_init(plat, TRUE);
  194. if (rc)
  195. sbi_hart_hang();
  196. if (!(scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS))
  197. sbi_boot_prints(scratch, hartid);
  198. wake_coldboot_harts(scratch, hartid);
  199. init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
  200. (*init_count)++;
  201. sbi_hsm_prepare_next_jump(scratch, hartid);
  202. sbi_hart_switch_mode(hartid, scratch->next_arg1, scratch->next_addr,
  203. scratch->next_mode, FALSE);
  204. }
  205. static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
  206. {
  207. int rc;
  208. unsigned long *init_count;
  209. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  210. wait_for_coldboot(scratch, hartid);
  211. if (!init_count_offset)
  212. sbi_hart_hang();
  213. rc = sbi_hsm_init(scratch, hartid, FALSE);
  214. if (rc)
  215. sbi_hart_hang();
  216. rc = sbi_platform_early_init(plat, FALSE);
  217. if (rc)
  218. sbi_hart_hang();
  219. rc = sbi_hart_init(scratch, FALSE);
  220. if (rc)
  221. sbi_hart_hang();
  222. rc = sbi_platform_irqchip_init(plat, FALSE);
  223. if (rc)
  224. sbi_hart_hang();
  225. rc = sbi_ipi_init(scratch, FALSE);
  226. if (rc)
  227. sbi_hart_hang();
  228. rc = sbi_tlb_init(scratch, FALSE);
  229. if (rc)
  230. sbi_hart_hang();
  231. rc = sbi_timer_init(scratch, FALSE);
  232. if (rc)
  233. sbi_hart_hang();
  234. rc = sbi_hart_pmp_configure(scratch);
  235. if (rc)
  236. sbi_hart_hang();
  237. rc = sbi_platform_final_init(plat, FALSE);
  238. if (rc)
  239. sbi_hart_hang();
  240. init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
  241. (*init_count)++;
  242. sbi_hsm_prepare_next_jump(scratch, hartid);
  243. sbi_hart_switch_mode(hartid, scratch->next_arg1,
  244. scratch->next_addr,
  245. scratch->next_mode, FALSE);
  246. }
  247. static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
  248. /**
  249. * Initialize OpenSBI library for current HART and jump to next
  250. * booting stage.
  251. *
  252. * The function expects following:
  253. * 1. The 'mscratch' CSR is pointing to sbi_scratch of current HART
  254. * 2. Stack pointer (SP) is setup for current HART
  255. * 3. Interrupts are disabled in MSTATUS CSR
  256. * 4. All interrupts are disabled in MIE CSR
  257. *
  258. * @param scratch pointer to sbi_scratch of current HART
  259. */
  260. void __noreturn sbi_init(struct sbi_scratch *scratch)
  261. {
  262. bool next_mode_supported = FALSE;
  263. bool coldboot = FALSE;
  264. u32 hartid = current_hartid();
  265. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  266. if ((SBI_HARTMASK_MAX_BITS <= hartid) ||
  267. sbi_platform_hart_invalid(plat, hartid))
  268. sbi_hart_hang();
  269. switch (scratch->next_mode) {
  270. case PRV_M:
  271. next_mode_supported = TRUE;
  272. break;
  273. case PRV_S:
  274. if (misa_extension('S'))
  275. next_mode_supported = TRUE;
  276. break;
  277. case PRV_U:
  278. if (misa_extension('U'))
  279. next_mode_supported = TRUE;
  280. break;
  281. default:
  282. sbi_hart_hang();
  283. }
  284. /*
  285. * Only the HART supporting privilege mode specified in the
  286. * scratch->next_mode should be allowed to become the coldboot
  287. * HART because the coldboot HART will be directly jumping to
  288. * the next booting stage.
  289. *
  290. * We use a lottery mechanism to select coldboot HART among
  291. * HARTs which satisfy above condition.
  292. */
  293. if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
  294. coldboot = TRUE;
  295. if (coldboot)
  296. init_coldboot(scratch, hartid);
  297. else
  298. init_warmboot(scratch, hartid);
  299. }
  300. unsigned long sbi_init_count(u32 hartid)
  301. {
  302. struct sbi_scratch *scratch;
  303. unsigned long *init_count;
  304. if (!init_count_offset)
  305. return 0;
  306. scratch = sbi_hartid_to_scratch(hartid);
  307. if (!scratch)
  308. return 0;
  309. init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
  310. return *init_count;
  311. }
  312. /**
  313. * Exit OpenSBI library for current HART and stop HART
  314. *
  315. * The function expects following:
  316. * 1. The 'mscratch' CSR is pointing to sbi_scratch of current HART
  317. * 2. Stack pointer (SP) is setup for current HART
  318. *
  319. * @param scratch pointer to sbi_scratch of current HART
  320. */
  321. void __noreturn sbi_exit(struct sbi_scratch *scratch)
  322. {
  323. u32 hartid = current_hartid();
  324. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  325. if (sbi_platform_hart_invalid(plat, hartid))
  326. sbi_hart_hang();
  327. sbi_platform_early_exit(plat);
  328. sbi_timer_exit(scratch);
  329. sbi_ipi_exit(scratch);
  330. sbi_platform_irqchip_exit(plat);
  331. sbi_platform_final_exit(plat);
  332. sbi_hsm_exit(scratch);
  333. }