sbi_pmu.c 24 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/sbi_bitops.h>
  11. #include <sbi/sbi_console.h>
  12. #include <sbi/sbi_ecall_interface.h>
  13. #include <sbi/sbi_hart.h>
  14. #include <sbi/sbi_hartmask.h>
  15. #include <sbi/sbi_platform.h>
  16. #include <sbi/sbi_pmu.h>
  17. #include <sbi/sbi_scratch.h>
  18. #include <sbi/sbi_string.h>
  19. /** Information about hardware counters */
  20. struct sbi_pmu_hw_event {
  21. uint32_t counters;
  22. uint32_t start_idx;
  23. uint32_t end_idx;
  24. /* Event selector value used only for raw events. The event select value
  25. * can be a even id or a selector value for set of events encoded in few
  26. * bits. In case latter, the bits used for encoding of the events should
  27. * be zeroed out in the select value.
  28. */
  29. uint64_t select;
  30. /**
  31. * The select_mask indicates which bits are encoded for the event(s).
  32. */
  33. uint64_t select_mask;
  34. };
  35. /* Information about PMU counters as per SBI specification */
  36. union sbi_pmu_ctr_info {
  37. unsigned long value;
  38. struct {
  39. unsigned long csr:12;
  40. unsigned long width:6;
  41. #if __riscv_xlen == 32
  42. unsigned long reserved:13;
  43. #else
  44. unsigned long reserved:45;
  45. #endif
  46. unsigned long type:1;
  47. };
  48. };
  49. /* Platform specific PMU device */
  50. static const struct sbi_pmu_device *pmu_dev = NULL;
  51. /* Mapping between event range and possible counters */
  52. static struct sbi_pmu_hw_event hw_event_map[SBI_PMU_HW_EVENT_MAX] = {0};
  53. /* counter to enabled event mapping */
  54. static uint32_t active_events[SBI_HARTMASK_MAX_BITS][SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX];
  55. /* Bitmap of firmware counters started on each HART */
  56. #if SBI_PMU_FW_CTR_MAX >= BITS_PER_LONG
  57. #error "Can't handle firmware counters beyond BITS_PER_LONG"
  58. #endif
  59. static unsigned long fw_counters_started[SBI_HARTMASK_MAX_BITS];
  60. /*
  61. * Counter values for SBI firmware events and event codes for platform
  62. * firmware events. Both are mutually exclusive and hence can optimally share
  63. * the same memory.
  64. */
  65. static uint64_t fw_counters_data[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_CTR_MAX] = {0};
  66. /* Maximum number of hardware events available */
  67. static uint32_t num_hw_events;
  68. /* Maximum number of hardware counters available */
  69. static uint32_t num_hw_ctrs;
  70. /* Maximum number of counters available */
  71. static uint32_t total_ctrs;
  72. /* Helper macros to retrieve event idx and code type */
  73. #define get_cidx_type(x) ((x & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16)
  74. #define get_cidx_code(x) (x & SBI_PMU_EVENT_IDX_CODE_MASK)
  75. /**
  76. * Perform a sanity check on event & counter mappings with event range overlap check
  77. * @param evtA Pointer to the existing hw event structure
  78. * @param evtB Pointer to the new hw event structure
  79. *
  80. * Return false if the range doesn't overlap, true otherwise
  81. */
  82. static bool pmu_event_range_overlap(struct sbi_pmu_hw_event *evtA,
  83. struct sbi_pmu_hw_event *evtB)
  84. {
  85. /* check if the range of events overlap with a previous entry */
  86. if (((evtA->end_idx < evtB->start_idx) && (evtA->end_idx < evtB->end_idx)) ||
  87. ((evtA->start_idx > evtB->start_idx) && (evtA->start_idx > evtB->end_idx)))
  88. return false;
  89. return true;
  90. }
  91. static bool pmu_event_select_overlap(struct sbi_pmu_hw_event *evt,
  92. uint64_t select_val, uint64_t select_mask)
  93. {
  94. if ((evt->select == select_val) && (evt->select_mask == select_mask))
  95. return true;
  96. return false;
  97. }
  98. static int pmu_event_validate(unsigned long event_idx, uint64_t edata)
  99. {
  100. uint32_t event_idx_type = get_cidx_type(event_idx);
  101. uint32_t event_idx_code = get_cidx_code(event_idx);
  102. uint32_t event_idx_code_max = -1;
  103. uint32_t cache_ops_result, cache_ops_id, cache_id;
  104. switch(event_idx_type) {
  105. case SBI_PMU_EVENT_TYPE_HW:
  106. event_idx_code_max = SBI_PMU_HW_GENERAL_MAX;
  107. break;
  108. case SBI_PMU_EVENT_TYPE_FW:
  109. if (SBI_PMU_FW_MAX <= event_idx_code &&
  110. pmu_dev && pmu_dev->fw_event_validate_encoding)
  111. return pmu_dev->fw_event_validate_encoding(edata);
  112. else
  113. event_idx_code_max = SBI_PMU_FW_MAX;
  114. break;
  115. case SBI_PMU_EVENT_TYPE_HW_CACHE:
  116. cache_ops_result = event_idx_code &
  117. SBI_PMU_EVENT_HW_CACHE_OPS_RESULT;
  118. cache_ops_id = (event_idx_code &
  119. SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK) >>
  120. SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET;
  121. cache_id = (event_idx_code &
  122. SBI_PMU_EVENT_HW_CACHE_ID_MASK) >>
  123. SBI_PMU_EVENT_HW_CACHE_ID_OFFSET;
  124. if ((cache_ops_result < SBI_PMU_HW_CACHE_RESULT_MAX) &&
  125. (cache_ops_id < SBI_PMU_HW_CACHE_OP_MAX) &&
  126. (cache_id < SBI_PMU_HW_CACHE_MAX))
  127. return event_idx_type;
  128. else
  129. return SBI_EINVAL;
  130. break;
  131. case SBI_PMU_EVENT_TYPE_HW_RAW:
  132. event_idx_code_max = 1; // event_idx.code should be zero
  133. break;
  134. default:
  135. return SBI_EINVAL;
  136. }
  137. if (event_idx_code < event_idx_code_max)
  138. return event_idx_type;
  139. return SBI_EINVAL;
  140. }
  141. static int pmu_ctr_validate(uint32_t cidx, uint32_t *event_idx_code)
  142. {
  143. uint32_t event_idx_val;
  144. uint32_t event_idx_type;
  145. u32 hartid = current_hartid();
  146. if (cidx >= total_ctrs)
  147. return SBI_EINVAL;
  148. event_idx_val = active_events[hartid][cidx];
  149. event_idx_type = get_cidx_type(event_idx_val);
  150. if (event_idx_val == SBI_PMU_EVENT_IDX_INVALID ||
  151. event_idx_type >= SBI_PMU_EVENT_TYPE_MAX)
  152. return SBI_EINVAL;
  153. *event_idx_code = get_cidx_code(event_idx_val);
  154. return event_idx_type;
  155. }
  156. int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval)
  157. {
  158. int event_idx_type;
  159. uint32_t event_code;
  160. u32 hartid = current_hartid();
  161. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  162. if (event_idx_type != SBI_PMU_EVENT_TYPE_FW)
  163. return SBI_EINVAL;
  164. if (SBI_PMU_FW_MAX <= event_code &&
  165. pmu_dev && pmu_dev->fw_counter_read_value)
  166. fw_counters_data[hartid][cidx - num_hw_ctrs] =
  167. pmu_dev->fw_counter_read_value(cidx - num_hw_ctrs);
  168. *cval = fw_counters_data[hartid][cidx - num_hw_ctrs];
  169. return 0;
  170. }
  171. static int pmu_add_hw_event_map(u32 eidx_start, u32 eidx_end, u32 cmap,
  172. uint64_t select, uint64_t select_mask)
  173. {
  174. int i = 0;
  175. bool is_overlap;
  176. struct sbi_pmu_hw_event *event = &hw_event_map[num_hw_events];
  177. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  178. int hw_ctr_avail = sbi_hart_mhpm_count(scratch);
  179. uint32_t ctr_avail_mask = ((uint32_t)(~0) >> (32 - (hw_ctr_avail + 3)));
  180. /* The first two counters are reserved by priv spec */
  181. if (eidx_start > SBI_PMU_HW_INSTRUCTIONS && (cmap & SBI_PMU_FIXED_CTR_MASK))
  182. return SBI_EDENIED;
  183. if (num_hw_events >= SBI_PMU_HW_EVENT_MAX - 1) {
  184. sbi_printf("Can not handle more than %d perf events\n",
  185. SBI_PMU_HW_EVENT_MAX);
  186. return SBI_EFAIL;
  187. }
  188. event->start_idx = eidx_start;
  189. event->end_idx = eidx_end;
  190. /* Sanity check */
  191. for (i = 0; i < num_hw_events; i++) {
  192. if (eidx_start == SBI_PMU_EVENT_RAW_IDX)
  193. /* All raw events have same event idx. Just do sanity check on select */
  194. is_overlap = pmu_event_select_overlap(&hw_event_map[i],
  195. select, select_mask);
  196. else
  197. is_overlap = pmu_event_range_overlap(&hw_event_map[i], event);
  198. if (is_overlap)
  199. goto reset_event;
  200. }
  201. event->select_mask = select_mask;
  202. /* Map the only the counters that are available in the hardware */
  203. event->counters = cmap & ctr_avail_mask;
  204. event->select = select;
  205. num_hw_events++;
  206. return 0;
  207. reset_event:
  208. event->start_idx = 0;
  209. event->end_idx = 0;
  210. return SBI_EINVAL;
  211. }
  212. /**
  213. * Logical counter ids are assigned to hardware counters are assigned consecutively.
  214. * E.g. counter0 must count MCYCLE where counter2 must count minstret. Similarly,
  215. * counterX will mhpmcounterX.
  216. */
  217. int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap)
  218. {
  219. if ((eidx_start > eidx_end) || eidx_start == SBI_PMU_EVENT_RAW_IDX ||
  220. eidx_end == SBI_PMU_EVENT_RAW_IDX)
  221. return SBI_EINVAL;
  222. return pmu_add_hw_event_map(eidx_start, eidx_end, cmap, 0, 0);
  223. }
  224. int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap)
  225. {
  226. return pmu_add_hw_event_map(SBI_PMU_EVENT_RAW_IDX,
  227. SBI_PMU_EVENT_RAW_IDX, cmap, select, select_mask);
  228. }
  229. static int pmu_ctr_enable_irq_hw(int ctr_idx)
  230. {
  231. unsigned long mhpmevent_csr;
  232. unsigned long mhpmevent_curr;
  233. unsigned long mip_val;
  234. unsigned long of_mask;
  235. if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  236. return SBI_EFAIL;
  237. #if __riscv_xlen == 32
  238. mhpmevent_csr = CSR_MHPMEVENT3H + ctr_idx - 3;
  239. of_mask = (uint32_t)~MHPMEVENTH_OF;
  240. #else
  241. mhpmevent_csr = CSR_MHPMEVENT3 + ctr_idx - 3;
  242. of_mask = ~MHPMEVENT_OF;
  243. #endif
  244. mhpmevent_curr = csr_read_num(mhpmevent_csr);
  245. mip_val = csr_read(CSR_MIP);
  246. /**
  247. * Clear out the OF bit so that next interrupt can be enabled.
  248. * This should be done only when the corresponding overflow interrupt
  249. * bit is cleared. That indicates that software has already handled the
  250. * previous interrupts or the hardware yet to set an overflow interrupt.
  251. * Otherwise, there will be race conditions where we may clear the bit
  252. * the software is yet to handle the interrupt.
  253. */
  254. if (!(mip_val & MIP_LCOFIP)) {
  255. mhpmevent_curr &= of_mask;
  256. csr_write_num(mhpmevent_csr, mhpmevent_curr);
  257. }
  258. return 0;
  259. }
  260. static void pmu_ctr_write_hw(uint32_t cidx, uint64_t ival)
  261. {
  262. #if __riscv_xlen == 32
  263. csr_write_num(CSR_MCYCLE + cidx, 0);
  264. csr_write_num(CSR_MCYCLE + cidx, ival & 0xFFFFFFFF);
  265. csr_write_num(CSR_MCYCLEH + cidx, ival >> BITS_PER_LONG);
  266. #else
  267. csr_write_num(CSR_MCYCLE + cidx, ival);
  268. #endif
  269. }
  270. static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
  271. {
  272. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  273. unsigned long mctr_inhbt;
  274. /* Make sure the counter index lies within the range and is not TM bit */
  275. if (cidx >= num_hw_ctrs || cidx == 1)
  276. return SBI_EINVAL;
  277. if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
  278. goto skip_inhibit_update;
  279. /*
  280. * Some of the hardware may not support mcountinhibit but perf stat
  281. * still can work if supervisor mode programs the initial value.
  282. */
  283. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  284. if (!__test_bit(cidx, &mctr_inhbt))
  285. return SBI_EALREADY_STARTED;
  286. __clear_bit(cidx, &mctr_inhbt);
  287. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  288. pmu_ctr_enable_irq_hw(cidx);
  289. if (pmu_dev && pmu_dev->hw_counter_enable_irq)
  290. pmu_dev->hw_counter_enable_irq(cidx);
  291. csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt);
  292. skip_inhibit_update:
  293. if (ival_update)
  294. pmu_ctr_write_hw(cidx, ival);
  295. return 0;
  296. }
  297. int sbi_pmu_irq_bit(void)
  298. {
  299. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  300. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  301. return MIP_LCOFIP;
  302. if (pmu_dev && pmu_dev->hw_counter_irq_bit)
  303. return pmu_dev->hw_counter_irq_bit();
  304. return 0;
  305. }
  306. static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code,
  307. uint64_t event_data, uint64_t ival,
  308. bool ival_update)
  309. {
  310. int ret;
  311. u32 hartid = current_hartid();
  312. if (SBI_PMU_FW_MAX <= event_code &&
  313. pmu_dev && pmu_dev->fw_counter_start) {
  314. ret = pmu_dev->fw_counter_start(cidx - num_hw_ctrs,
  315. event_data,
  316. ival, ival_update);
  317. if (ret)
  318. return ret;
  319. }
  320. if (ival_update)
  321. fw_counters_data[hartid][cidx - num_hw_ctrs] = ival;
  322. fw_counters_started[hartid] |= BIT(cidx - num_hw_ctrs);
  323. return 0;
  324. }
  325. int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask,
  326. unsigned long flags, uint64_t ival)
  327. {
  328. int event_idx_type;
  329. uint32_t event_code;
  330. int ret = SBI_EINVAL;
  331. bool bUpdate = false;
  332. int i, cidx;
  333. uint64_t edata = 0;
  334. if ((cbase + sbi_fls(cmask)) >= total_ctrs)
  335. return ret;
  336. if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE)
  337. bUpdate = true;
  338. for_each_set_bit(i, &cmask, total_ctrs) {
  339. cidx = i + cbase;
  340. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  341. if (event_idx_type < 0)
  342. /* Continue the start operation for other counters */
  343. continue;
  344. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
  345. ret = pmu_ctr_start_fw(cidx, event_code, edata, ival,
  346. bUpdate);
  347. else
  348. ret = pmu_ctr_start_hw(cidx, ival, bUpdate);
  349. }
  350. return ret;
  351. }
  352. static int pmu_ctr_stop_hw(uint32_t cidx)
  353. {
  354. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  355. unsigned long mctr_inhbt;
  356. if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
  357. return 0;
  358. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  359. /* Make sure the counter index lies within the range and is not TM bit */
  360. if (cidx >= num_hw_ctrs || cidx == 1)
  361. return SBI_EINVAL;
  362. if (!__test_bit(cidx, &mctr_inhbt)) {
  363. __set_bit(cidx, &mctr_inhbt);
  364. csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt);
  365. return 0;
  366. } else
  367. return SBI_EALREADY_STOPPED;
  368. }
  369. static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t event_code)
  370. {
  371. int ret;
  372. if (SBI_PMU_FW_MAX <= event_code &&
  373. pmu_dev && pmu_dev->fw_counter_stop) {
  374. ret = pmu_dev->fw_counter_stop(cidx - num_hw_ctrs);
  375. if (ret)
  376. return ret;
  377. }
  378. fw_counters_started[current_hartid()] &= ~BIT(cidx - num_hw_ctrs);
  379. return 0;
  380. }
  381. static int pmu_reset_hw_mhpmevent(int ctr_idx)
  382. {
  383. if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  384. return SBI_EFAIL;
  385. #if __riscv_xlen == 32
  386. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0);
  387. if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
  388. SBI_HART_EXT_SSCOFPMF))
  389. csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, 0);
  390. #else
  391. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0);
  392. #endif
  393. return 0;
  394. }
  395. int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask,
  396. unsigned long flag)
  397. {
  398. u32 hartid = current_hartid();
  399. int ret = SBI_EINVAL;
  400. int event_idx_type;
  401. uint32_t event_code;
  402. int i, cidx;
  403. if ((cbase + sbi_fls(cmask)) >= total_ctrs)
  404. return SBI_EINVAL;
  405. for_each_set_bit(i, &cmask, total_ctrs) {
  406. cidx = i + cbase;
  407. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  408. if (event_idx_type < 0)
  409. /* Continue the stop operation for other counters */
  410. continue;
  411. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
  412. ret = pmu_ctr_stop_fw(cidx, event_code);
  413. else
  414. ret = pmu_ctr_stop_hw(cidx);
  415. if (flag & SBI_PMU_STOP_FLAG_RESET) {
  416. active_events[hartid][cidx] = SBI_PMU_EVENT_IDX_INVALID;
  417. pmu_reset_hw_mhpmevent(cidx);
  418. }
  419. }
  420. return ret;
  421. }
  422. static void pmu_update_inhibit_flags(unsigned long flags, uint64_t *mhpmevent_val)
  423. {
  424. if (flags & SBI_PMU_CFG_FLAG_SET_VUINH)
  425. *mhpmevent_val |= MHPMEVENT_VUINH;
  426. if (flags & SBI_PMU_CFG_FLAG_SET_VSINH)
  427. *mhpmevent_val |= MHPMEVENT_VSINH;
  428. if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
  429. *mhpmevent_val |= MHPMEVENT_UINH;
  430. if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
  431. *mhpmevent_val |= MHPMEVENT_SINH;
  432. }
  433. static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
  434. unsigned long flags, unsigned long eindex,
  435. uint64_t data)
  436. {
  437. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  438. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  439. uint64_t mhpmevent_val;
  440. /* Get the final mhpmevent value to be written from platform */
  441. mhpmevent_val = sbi_platform_pmu_xlate_to_mhpmevent(plat, eindex, data);
  442. if (!mhpmevent_val || ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  443. return SBI_EFAIL;
  444. /**
  445. * Always set the OVF bit(disable interrupts) and inhibit counting of
  446. * events in M-mode. The OVF bit should be enabled during the start call.
  447. */
  448. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  449. mhpmevent_val = (mhpmevent_val & ~MHPMEVENT_SSCOF_MASK) |
  450. MHPMEVENT_MINH | MHPMEVENT_OF;
  451. if (pmu_dev && pmu_dev->hw_counter_disable_irq)
  452. pmu_dev->hw_counter_disable_irq(ctr_idx);
  453. /* Update the inhibit flags based on inhibit flags received from supervisor */
  454. pmu_update_inhibit_flags(flags, &mhpmevent_val);
  455. #if __riscv_xlen == 32
  456. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
  457. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  458. csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3,
  459. mhpmevent_val >> BITS_PER_LONG);
  460. #else
  461. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val);
  462. #endif
  463. return 0;
  464. }
  465. static int pmu_ctr_find_fixed_fw(unsigned long evt_idx_code)
  466. {
  467. /* Non-programmables counters are enabled always. No need to do lookup */
  468. if (evt_idx_code == SBI_PMU_HW_CPU_CYCLES)
  469. return 0;
  470. else if (evt_idx_code == SBI_PMU_HW_INSTRUCTIONS)
  471. return 2;
  472. else
  473. return SBI_EINVAL;
  474. }
  475. static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned long flags,
  476. unsigned long event_idx, uint64_t data)
  477. {
  478. unsigned long ctr_mask;
  479. int i, ret = 0, fixed_ctr, ctr_idx = SBI_ENOTSUPP;
  480. struct sbi_pmu_hw_event *temp;
  481. unsigned long mctr_inhbt = 0;
  482. u32 hartid = current_hartid();
  483. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  484. if (cbase >= num_hw_ctrs)
  485. return SBI_EINVAL;
  486. /**
  487. * If Sscof is present try to find the programmable counter for
  488. * cycle/instret as well.
  489. */
  490. fixed_ctr = pmu_ctr_find_fixed_fw(event_idx);
  491. if (fixed_ctr >= 0 &&
  492. !sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  493. return fixed_ctr;
  494. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11)
  495. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  496. for (i = 0; i < num_hw_events; i++) {
  497. temp = &hw_event_map[i];
  498. if ((temp->start_idx > event_idx && event_idx < temp->end_idx) ||
  499. (temp->start_idx < event_idx && event_idx > temp->end_idx))
  500. continue;
  501. /* For raw events, event data is used as the select value */
  502. if (event_idx == SBI_PMU_EVENT_RAW_IDX) {
  503. uint64_t select_mask = temp->select_mask;
  504. /* The non-event map bits of data should match the selector */
  505. if (temp->select != (data & select_mask))
  506. continue;
  507. }
  508. /* Fixed counters should not be part of the search */
  509. ctr_mask = temp->counters & (cmask << cbase) &
  510. (~SBI_PMU_FIXED_CTR_MASK);
  511. for_each_set_bit_from(cbase, &ctr_mask, SBI_PMU_HW_CTR_MAX) {
  512. /**
  513. * Some of the platform may not support mcountinhibit.
  514. * Checking the active_events is enough for them
  515. */
  516. if (active_events[hartid][cbase] != SBI_PMU_EVENT_IDX_INVALID)
  517. continue;
  518. /* If mcountinhibit is supported, the bit must be enabled */
  519. if ((sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11) &&
  520. !__test_bit(cbase, &mctr_inhbt))
  521. continue;
  522. /* We found a valid counter that is not started yet */
  523. ctr_idx = cbase;
  524. }
  525. }
  526. if (ctr_idx == SBI_ENOTSUPP) {
  527. /**
  528. * We can't find any programmable counters for cycle/instret.
  529. * Return the fixed counter as they are mandatory anyways.
  530. */
  531. if (fixed_ctr >= 0)
  532. return fixed_ctr;
  533. else
  534. return SBI_EFAIL;
  535. }
  536. ret = pmu_update_hw_mhpmevent(temp, ctr_idx, flags, event_idx, data);
  537. if (!ret)
  538. ret = ctr_idx;
  539. return ret;
  540. }
  541. /**
  542. * Any firmware counter can map to any firmware event.
  543. * Thus, select the first available fw counter after sanity
  544. * check.
  545. */
  546. static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask,
  547. uint32_t event_code, u32 hartid, uint64_t edata)
  548. {
  549. int i, cidx;
  550. for_each_set_bit(i, &cmask, BITS_PER_LONG) {
  551. cidx = i + cbase;
  552. if (cidx < num_hw_ctrs || total_ctrs <= cidx)
  553. continue;
  554. if (active_events[hartid][i] != SBI_PMU_EVENT_IDX_INVALID)
  555. continue;
  556. if (SBI_PMU_FW_MAX <= event_code &&
  557. pmu_dev && pmu_dev->fw_counter_match_encoding) {
  558. if (!pmu_dev->fw_counter_match_encoding(cidx - num_hw_ctrs,
  559. edata))
  560. continue;
  561. }
  562. return i;
  563. }
  564. return SBI_ENOTSUPP;
  565. }
  566. int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
  567. unsigned long flags, unsigned long event_idx,
  568. uint64_t event_data)
  569. {
  570. int ret, ctr_idx = SBI_ENOTSUPP;
  571. u32 event_code, hartid = current_hartid();
  572. int event_type;
  573. /* Do a basic sanity check of counter base & mask */
  574. if ((cidx_base + sbi_fls(cidx_mask)) >= total_ctrs)
  575. return SBI_EINVAL;
  576. event_type = pmu_event_validate(event_idx, event_data);
  577. if (event_type < 0)
  578. return SBI_EINVAL;
  579. event_code = get_cidx_code(event_idx);
  580. if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) {
  581. /* The caller wants to skip the match because it already knows the
  582. * counter idx for the given event. Verify that the counter idx
  583. * is still valid.
  584. */
  585. if (active_events[hartid][cidx_base] == SBI_PMU_EVENT_IDX_INVALID)
  586. return SBI_EINVAL;
  587. ctr_idx = cidx_base;
  588. goto skip_match;
  589. }
  590. if (event_type == SBI_PMU_EVENT_TYPE_FW) {
  591. /* Any firmware counter can be used track any firmware event */
  592. ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code,
  593. hartid, event_data);
  594. } else {
  595. ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx,
  596. event_data);
  597. }
  598. if (ctr_idx < 0)
  599. return SBI_ENOTSUPP;
  600. active_events[hartid][ctr_idx] = event_idx;
  601. skip_match:
  602. if (event_type == SBI_PMU_EVENT_TYPE_HW) {
  603. if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE)
  604. pmu_ctr_write_hw(ctr_idx, 0);
  605. if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
  606. pmu_ctr_start_hw(ctr_idx, 0, false);
  607. } else if (event_type == SBI_PMU_EVENT_TYPE_FW) {
  608. if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE)
  609. fw_counters_data[hartid][ctr_idx - num_hw_ctrs] = 0;
  610. if (flags & SBI_PMU_CFG_FLAG_AUTO_START) {
  611. if (SBI_PMU_FW_MAX <= event_code &&
  612. pmu_dev && pmu_dev->fw_counter_start) {
  613. ret = pmu_dev->fw_counter_start(
  614. ctr_idx - num_hw_ctrs, event_data,
  615. fw_counters_data[hartid][ctr_idx - num_hw_ctrs],
  616. true);
  617. if (ret)
  618. return ret;
  619. }
  620. fw_counters_started[hartid] |= BIT(ctr_idx - num_hw_ctrs);
  621. }
  622. }
  623. return ctr_idx;
  624. }
  625. int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id)
  626. {
  627. u32 cidx, hartid = current_hartid();
  628. uint64_t *fcounter = NULL;
  629. if (likely(!fw_counters_started[hartid]))
  630. return 0;
  631. if (unlikely(fw_id >= SBI_PMU_FW_MAX))
  632. return SBI_EINVAL;
  633. for (cidx = num_hw_ctrs; cidx < total_ctrs; cidx++) {
  634. if (get_cidx_code(active_events[hartid][cidx]) == fw_id &&
  635. (fw_counters_started[hartid] & BIT(cidx - num_hw_ctrs))) {
  636. fcounter = &fw_counters_data[hartid][cidx - num_hw_ctrs];
  637. break;
  638. }
  639. }
  640. if (fcounter)
  641. (*fcounter)++;
  642. return 0;
  643. }
  644. unsigned long sbi_pmu_num_ctr(void)
  645. {
  646. return (num_hw_ctrs + SBI_PMU_FW_CTR_MAX);
  647. }
  648. int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info)
  649. {
  650. int width;
  651. union sbi_pmu_ctr_info cinfo = {0};
  652. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  653. /* Sanity check. Counter1 is not mapped at all */
  654. if (cidx >= total_ctrs || cidx == 1)
  655. return SBI_EINVAL;
  656. /* We have 31 HW counters with 31 being the last index(MHPMCOUNTER31) */
  657. if (cidx < num_hw_ctrs) {
  658. cinfo.type = SBI_PMU_CTR_TYPE_HW;
  659. cinfo.csr = CSR_CYCLE + cidx;
  660. /* mcycle & minstret are always 64 bit */
  661. if (cidx == 0 || cidx == 2)
  662. cinfo.width = 63;
  663. else
  664. cinfo.width = sbi_hart_mhpm_bits(scratch) - 1;
  665. } else {
  666. /* it's a firmware counter */
  667. cinfo.type = SBI_PMU_CTR_TYPE_FW;
  668. /* Firmware counters are always 64 bits wide */
  669. cinfo.width = 63;
  670. if (pmu_dev && pmu_dev->fw_counter_width) {
  671. width = pmu_dev->fw_counter_width();
  672. if (width)
  673. cinfo.width = width - 1;
  674. }
  675. }
  676. *ctr_info = cinfo.value;
  677. return 0;
  678. }
  679. static void pmu_reset_event_map(u32 hartid)
  680. {
  681. int j;
  682. /* Initialize the counter to event mapping table */
  683. for (j = 3; j < total_ctrs; j++)
  684. active_events[hartid][j] = SBI_PMU_EVENT_IDX_INVALID;
  685. for (j = 0; j < SBI_PMU_FW_CTR_MAX; j++)
  686. fw_counters_data[hartid][j] = 0;
  687. fw_counters_started[hartid] = 0;
  688. }
  689. const struct sbi_pmu_device *sbi_pmu_get_device(void)
  690. {
  691. return pmu_dev;
  692. }
  693. void sbi_pmu_set_device(const struct sbi_pmu_device *dev)
  694. {
  695. if (!dev || pmu_dev)
  696. return;
  697. pmu_dev = dev;
  698. }
  699. void sbi_pmu_exit(struct sbi_scratch *scratch)
  700. {
  701. u32 hartid = current_hartid();
  702. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11)
  703. csr_write(CSR_MCOUNTINHIBIT, 0xFFFFFFF8);
  704. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_10)
  705. csr_write(CSR_MCOUNTEREN, -1);
  706. pmu_reset_event_map(hartid);
  707. }
  708. int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
  709. {
  710. const struct sbi_platform *plat;
  711. u32 hartid = current_hartid();
  712. if (cold_boot) {
  713. plat = sbi_platform_ptr(scratch);
  714. /* Initialize hw pmu events */
  715. sbi_platform_pmu_init(plat);
  716. /* mcycle & minstret is available always */
  717. num_hw_ctrs = sbi_hart_mhpm_count(scratch) + 3;
  718. total_ctrs = num_hw_ctrs + SBI_PMU_FW_CTR_MAX;
  719. }
  720. pmu_reset_event_map(hartid);
  721. /* First three counters are fixed by the priv spec and we enable it by default */
  722. active_events[hartid][0] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET |
  723. SBI_PMU_HW_CPU_CYCLES;
  724. active_events[hartid][1] = SBI_PMU_EVENT_IDX_INVALID;
  725. active_events[hartid][2] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET |
  726. SBI_PMU_HW_INSTRUCTIONS;
  727. return 0;
  728. }