sbi_pmu.h 3.9 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #ifndef __SBI_PMU_H__
  10. #define __SBI_PMU_H__
  11. #include <sbi/sbi_types.h>
  12. struct sbi_scratch;
  13. /* Event related macros */
  14. /* Maximum number of hardware events that can mapped by OpenSBI */
  15. #define SBI_PMU_HW_EVENT_MAX 256
  16. /* Counter related macros */
  17. #define SBI_PMU_FW_CTR_MAX 16
  18. #define SBI_PMU_HW_CTR_MAX 32
  19. #define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX)
  20. #define SBI_PMU_FIXED_CTR_MASK 0x07
  21. struct sbi_pmu_device {
  22. /** Name of the PMU platform device */
  23. char name[32];
  24. /**
  25. * Validate event code of custom firmware event
  26. */
  27. int (*fw_event_validate_encoding)(uint64_t event_data);
  28. /**
  29. * Match custom firmware counter with custom firmware event
  30. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  31. */
  32. bool (*fw_counter_match_encoding)(uint32_t counter_index,
  33. uint64_t event_data);
  34. /**
  35. * Fetch the max width of this counter in number of bits.
  36. */
  37. int (*fw_counter_width)(void);
  38. /**
  39. * Read value of custom firmware counter
  40. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  41. */
  42. uint64_t (*fw_counter_read_value)(uint32_t counter_index);
  43. /**
  44. * Start custom firmware counter
  45. * Note: SBI_PMU_FW_MAX <= event_idx_code
  46. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  47. */
  48. int (*fw_counter_start)(uint32_t counter_index,
  49. uint64_t event_data,
  50. uint64_t init_val, bool init_val_update);
  51. /**
  52. * Stop custom firmware counter
  53. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  54. */
  55. int (*fw_counter_stop)(uint32_t counter_index);
  56. /**
  57. * Custom enable irq for hardware counter
  58. * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
  59. */
  60. void (*hw_counter_enable_irq)(uint32_t counter_index);
  61. /**
  62. * Custom disable irq for hardware counter
  63. * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
  64. */
  65. void (*hw_counter_disable_irq)(uint32_t counter_index);
  66. /**
  67. * Custom function returning the machine-specific irq-bit.
  68. */
  69. int (*hw_counter_irq_bit)(void);
  70. };
  71. /** Get the PMU platform device */
  72. const struct sbi_pmu_device *sbi_pmu_get_device(void);
  73. /** Set the PMU platform device */
  74. void sbi_pmu_set_device(const struct sbi_pmu_device *dev);
  75. /** Initialize PMU */
  76. int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
  77. /** Reset PMU during hart exit */
  78. void sbi_pmu_exit(struct sbi_scratch *scratch);
  79. /** Return the pmu irq bit depending on extension existence */
  80. int sbi_pmu_irq_bit(void);
  81. /**
  82. * Add the hardware event to counter mapping information. This should be called
  83. * from the platform code to update the mapping table.
  84. * @param eidx_start Start of the event idx range for supported counters
  85. * @param eidx_end End of the event idx range for supported counters
  86. * @param cmap A bitmap representing counters supporting the event range
  87. * @return 0 on success, error otherwise.
  88. */
  89. int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap);
  90. /**
  91. * Add the raw hardware event selector and supported counter information. This
  92. * should be called from the platform code to update the mapping table.
  93. * @param info a pointer to the hardware event info
  94. * @return 0 on success, error otherwise.
  95. */
  96. int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap);
  97. int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval);
  98. int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask,
  99. unsigned long flag);
  100. int sbi_pmu_ctr_start(unsigned long cidx_base, unsigned long cidx_mask,
  101. unsigned long flags, uint64_t ival);
  102. int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info);
  103. unsigned long sbi_pmu_num_ctr(void);
  104. int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
  105. unsigned long flags, unsigned long event_idx,
  106. uint64_t event_data);
  107. int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id);
  108. #endif