sbi_hsm.c 13 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2020 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_barrier.h>
  11. #include <sbi/riscv_encoding.h>
  12. #include <sbi/riscv_atomic.h>
  13. #include <sbi/sbi_bitops.h>
  14. #include <sbi/sbi_console.h>
  15. #include <sbi/sbi_domain.h>
  16. #include <sbi/sbi_error.h>
  17. #include <sbi/sbi_ecall_interface.h>
  18. #include <sbi/sbi_hart.h>
  19. #include <sbi/sbi_hartmask.h>
  20. #include <sbi/sbi_hsm.h>
  21. #include <sbi/sbi_init.h>
  22. #include <sbi/sbi_ipi.h>
  23. #include <sbi/sbi_scratch.h>
  24. #include <sbi/sbi_system.h>
  25. #include <sbi/sbi_timer.h>
  26. #include <sbi/sbi_console.h>
  27. #define __sbi_hsm_hart_change_state(hdata, oldstate, newstate) \
  28. ({ \
  29. long state = atomic_cmpxchg(&(hdata)->state, oldstate, newstate); \
  30. if (state != (oldstate)) \
  31. sbi_printf("%s: ERR: The hart is in invalid state [%lu]\n", \
  32. __func__, state); \
  33. state == (oldstate); \
  34. })
  35. static const struct sbi_hsm_device *hsm_dev = NULL;
  36. static unsigned long hart_data_offset;
  37. /** Per hart specific data to manage state transition **/
  38. struct sbi_hsm_data {
  39. atomic_t state;
  40. unsigned long suspend_type;
  41. unsigned long saved_mie;
  42. unsigned long saved_mip;
  43. };
  44. static inline int __sbi_hsm_hart_get_state(u32 hartid)
  45. {
  46. struct sbi_hsm_data *hdata;
  47. struct sbi_scratch *scratch;
  48. scratch = sbi_hartid_to_scratch(hartid);
  49. if (!scratch)
  50. return SBI_EINVAL;
  51. hdata = sbi_scratch_offset_ptr(scratch, hart_data_offset);
  52. return atomic_read(&hdata->state);
  53. }
  54. int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid)
  55. {
  56. if (!sbi_domain_is_assigned_hart(dom, hartid))
  57. return SBI_EINVAL;
  58. return __sbi_hsm_hart_get_state(hartid);
  59. }
  60. /**
  61. * Get ulong HART mask for given HART base ID
  62. * @param dom the domain to be used for output HART mask
  63. * @param hbase the HART base ID
  64. * @param out_hmask the output ulong HART mask
  65. * @return 0 on success and SBI_Exxx (< 0) on failure
  66. * Note: the output HART mask will be set to zero on failure as well.
  67. */
  68. int sbi_hsm_hart_interruptible_mask(const struct sbi_domain *dom,
  69. ulong hbase, ulong *out_hmask)
  70. {
  71. int hstate;
  72. ulong i, hmask, dmask;
  73. ulong hend = sbi_scratch_last_hartid() + 1;
  74. *out_hmask = 0;
  75. if (hend <= hbase)
  76. return SBI_EINVAL;
  77. if (BITS_PER_LONG < (hend - hbase))
  78. hend = hbase + BITS_PER_LONG;
  79. dmask = sbi_domain_get_assigned_hartmask(dom, hbase);
  80. for (i = hbase; i < hend; i++) {
  81. hmask = 1UL << (i - hbase);
  82. if (dmask & hmask) {
  83. hstate = __sbi_hsm_hart_get_state(i);
  84. if (hstate == SBI_HSM_STATE_STARTED ||
  85. hstate == SBI_HSM_STATE_SUSPENDED)
  86. *out_hmask |= hmask;
  87. }
  88. }
  89. return 0;
  90. }
  91. void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid)
  92. {
  93. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  94. hart_data_offset);
  95. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_START_PENDING,
  96. SBI_HSM_STATE_STARTED))
  97. sbi_hart_hang();
  98. }
  99. static void sbi_hsm_hart_wait(struct sbi_scratch *scratch, u32 hartid)
  100. {
  101. unsigned long saved_mie;
  102. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  103. hart_data_offset);
  104. /* Save MIE CSR */
  105. saved_mie = csr_read(CSR_MIE);
  106. /* Set MSIE and MEIE bits to receive IPI */
  107. csr_set(CSR_MIE, MIP_MSIP | MIP_MEIP);
  108. /* Wait for state transition requested by sbi_hsm_hart_start() */
  109. while (atomic_read(&hdata->state) != SBI_HSM_STATE_START_PENDING) {
  110. wfi();
  111. };
  112. /* Restore MIE CSR */
  113. csr_write(CSR_MIE, saved_mie);
  114. /*
  115. * No need to clear IPI here because the sbi_ipi_init() will
  116. * clear it for current HART via sbi_platform_ipi_init().
  117. */
  118. }
  119. const struct sbi_hsm_device *sbi_hsm_get_device(void)
  120. {
  121. return hsm_dev;
  122. }
  123. void sbi_hsm_set_device(const struct sbi_hsm_device *dev)
  124. {
  125. if (!dev || hsm_dev)
  126. return;
  127. hsm_dev = dev;
  128. }
  129. static bool hsm_device_has_hart_hotplug(void)
  130. {
  131. if (hsm_dev && hsm_dev->hart_start && hsm_dev->hart_stop)
  132. return true;
  133. return false;
  134. }
  135. static bool hsm_device_has_hart_secondary_boot(void)
  136. {
  137. if (hsm_dev && hsm_dev->hart_start && !hsm_dev->hart_stop)
  138. return true;
  139. return false;
  140. }
  141. static int hsm_device_hart_start(u32 hartid, ulong saddr)
  142. {
  143. if (hsm_dev && hsm_dev->hart_start)
  144. return hsm_dev->hart_start(hartid, saddr);
  145. return SBI_ENOTSUPP;
  146. }
  147. static int hsm_device_hart_stop(void)
  148. {
  149. if (hsm_dev && hsm_dev->hart_stop)
  150. return hsm_dev->hart_stop();
  151. return SBI_ENOTSUPP;
  152. }
  153. static int hsm_device_hart_suspend(u32 suspend_type)
  154. {
  155. if (hsm_dev && hsm_dev->hart_suspend)
  156. return hsm_dev->hart_suspend(suspend_type);
  157. return SBI_ENOTSUPP;
  158. }
  159. static void hsm_device_hart_resume(void)
  160. {
  161. if (hsm_dev && hsm_dev->hart_resume)
  162. hsm_dev->hart_resume();
  163. }
  164. int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
  165. {
  166. u32 i;
  167. struct sbi_scratch *rscratch;
  168. struct sbi_hsm_data *hdata;
  169. if (cold_boot) {
  170. hart_data_offset = sbi_scratch_alloc_offset(sizeof(*hdata));
  171. if (!hart_data_offset)
  172. return SBI_ENOMEM;
  173. /* Initialize hart state data for every hart */
  174. for (i = 0; i <= sbi_scratch_last_hartid(); i++) {
  175. rscratch = sbi_hartid_to_scratch(i);
  176. if (!rscratch)
  177. continue;
  178. hdata = sbi_scratch_offset_ptr(rscratch,
  179. hart_data_offset);
  180. ATOMIC_INIT(&hdata->state,
  181. (i == hartid) ?
  182. SBI_HSM_STATE_START_PENDING :
  183. SBI_HSM_STATE_STOPPED);
  184. }
  185. } else {
  186. sbi_hsm_hart_wait(scratch, hartid);
  187. }
  188. return 0;
  189. }
  190. void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch)
  191. {
  192. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  193. hart_data_offset);
  194. void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;
  195. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_STOP_PENDING,
  196. SBI_HSM_STATE_STOPPED))
  197. goto fail_exit;
  198. if (hsm_device_has_hart_hotplug()) {
  199. if (hsm_device_hart_stop() != SBI_ENOTSUPP)
  200. goto fail_exit;
  201. }
  202. /**
  203. * As platform is lacking support for hotplug, directly jump to warmboot
  204. * and wait for interrupts in warmboot. We do it preemptively in order
  205. * preserve the hart states and reuse the code path for hotplug.
  206. */
  207. jump_warmboot();
  208. fail_exit:
  209. /* It should never reach here */
  210. sbi_printf("ERR: Failed stop hart [%u]\n", current_hartid());
  211. sbi_hart_hang();
  212. }
  213. int sbi_hsm_hart_start(struct sbi_scratch *scratch,
  214. const struct sbi_domain *dom,
  215. u32 hartid, ulong saddr, ulong smode, ulong arg1)
  216. {
  217. unsigned long init_count;
  218. unsigned int hstate;
  219. struct sbi_scratch *rscratch;
  220. struct sbi_hsm_data *hdata;
  221. /* For now, we only allow start mode to be S-mode or U-mode. */
  222. if (smode != PRV_S && smode != PRV_U)
  223. return SBI_EINVAL;
  224. if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
  225. return SBI_EINVAL;
  226. if (dom && !sbi_domain_check_addr(dom, saddr, smode,
  227. SBI_DOMAIN_EXECUTE))
  228. return SBI_EINVALID_ADDR;
  229. rscratch = sbi_hartid_to_scratch(hartid);
  230. if (!rscratch)
  231. return SBI_EINVAL;
  232. hdata = sbi_scratch_offset_ptr(rscratch, hart_data_offset);
  233. hstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_STOPPED,
  234. SBI_HSM_STATE_START_PENDING);
  235. if (hstate == SBI_HSM_STATE_STARTED)
  236. return SBI_EALREADY;
  237. /**
  238. * if a hart is already transition to start or stop, another start call
  239. * is considered as invalid request.
  240. */
  241. if (hstate != SBI_HSM_STATE_STOPPED)
  242. return SBI_EINVAL;
  243. init_count = sbi_init_count(hartid);
  244. rscratch->next_arg1 = arg1;
  245. rscratch->next_addr = saddr;
  246. rscratch->next_mode = smode;
  247. if (hsm_device_has_hart_hotplug() ||
  248. (hsm_device_has_hart_secondary_boot() && !init_count)) {
  249. return hsm_device_hart_start(hartid, scratch->warmboot_addr);
  250. } else {
  251. int rc = sbi_ipi_raw_send(hartid);
  252. if (rc)
  253. return rc;
  254. }
  255. return 0;
  256. }
  257. int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow)
  258. {
  259. const struct sbi_domain *dom = sbi_domain_thishart_ptr();
  260. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  261. hart_data_offset);
  262. if (!dom)
  263. return SBI_EFAIL;
  264. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_STARTED,
  265. SBI_HSM_STATE_STOP_PENDING))
  266. return SBI_EFAIL;
  267. if (exitnow)
  268. sbi_exit(scratch);
  269. return 0;
  270. }
  271. static int __sbi_hsm_suspend_default(struct sbi_scratch *scratch)
  272. {
  273. /* Wait for interrupt */
  274. wfi();
  275. return 0;
  276. }
  277. static void __sbi_hsm_suspend_non_ret_save(struct sbi_scratch *scratch)
  278. {
  279. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  280. hart_data_offset);
  281. /*
  282. * We will be resuming in warm-boot path so the MIE and MIP CSRs
  283. * will be back to initial state. It is possible that HART has
  284. * configured timer event before going to suspend state so we
  285. * should save MIE and MIP CSRs and restore it after resuming.
  286. *
  287. * Further, the M-mode bits in MIP CSR are read-only and set by
  288. * external devices (such as interrupt controller) whereas all
  289. * VS-mode bits in MIP are read-only alias of bits in HVIP CSR.
  290. *
  291. * This means we should only save/restore S-mode bits of MIP CSR
  292. * such as MIP.SSIP and MIP.STIP.
  293. */
  294. hdata->saved_mie = csr_read(CSR_MIE);
  295. hdata->saved_mip = csr_read(CSR_MIP) & (MIP_SSIP | MIP_STIP);
  296. }
  297. static void __sbi_hsm_suspend_non_ret_restore(struct sbi_scratch *scratch)
  298. {
  299. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  300. hart_data_offset);
  301. csr_write(CSR_MIE, hdata->saved_mie);
  302. csr_set(CSR_MIP, (hdata->saved_mip & (MIP_SSIP | MIP_STIP)));
  303. }
  304. void sbi_hsm_hart_resume_start(struct sbi_scratch *scratch)
  305. {
  306. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  307. hart_data_offset);
  308. /* If current HART was SUSPENDED then set RESUME_PENDING state */
  309. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_SUSPENDED,
  310. SBI_HSM_STATE_RESUME_PENDING))
  311. sbi_hart_hang();
  312. hsm_device_hart_resume();
  313. }
  314. void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch)
  315. {
  316. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  317. hart_data_offset);
  318. /* If current HART was RESUME_PENDING then set STARTED state */
  319. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_RESUME_PENDING,
  320. SBI_HSM_STATE_STARTED))
  321. sbi_hart_hang();
  322. /*
  323. * Restore some of the M-mode CSRs which we are re-configured by
  324. * the warm-boot sequence.
  325. */
  326. __sbi_hsm_suspend_non_ret_restore(scratch);
  327. }
  328. int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
  329. ulong raddr, ulong rmode, ulong arg1)
  330. {
  331. int ret;
  332. const struct sbi_domain *dom = sbi_domain_thishart_ptr();
  333. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  334. hart_data_offset);
  335. /* Sanity check on domain assigned to current HART */
  336. if (!dom)
  337. return SBI_EFAIL;
  338. /* Sanity check on suspend type */
  339. if (SBI_HSM_SUSPEND_RET_DEFAULT < suspend_type &&
  340. suspend_type < SBI_HSM_SUSPEND_RET_PLATFORM)
  341. return SBI_EINVAL;
  342. if (SBI_HSM_SUSPEND_NON_RET_DEFAULT < suspend_type &&
  343. suspend_type < SBI_HSM_SUSPEND_NON_RET_PLATFORM)
  344. return SBI_EINVAL;
  345. /* Additional sanity check for non-retentive suspend */
  346. if (suspend_type & SBI_HSM_SUSP_NON_RET_BIT) {
  347. /*
  348. * For now, we only allow non-retentive suspend from
  349. * S-mode or U-mode.
  350. */
  351. if (rmode != PRV_S && rmode != PRV_U)
  352. return SBI_EFAIL;
  353. if (dom && !sbi_domain_check_addr(dom, raddr, rmode,
  354. SBI_DOMAIN_EXECUTE))
  355. return SBI_EINVALID_ADDR;
  356. }
  357. /* Save the resume address and resume mode */
  358. scratch->next_arg1 = arg1;
  359. scratch->next_addr = raddr;
  360. scratch->next_mode = rmode;
  361. /* Directly move from STARTED to SUSPENDED state */
  362. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_STARTED,
  363. SBI_HSM_STATE_SUSPENDED))
  364. return SBI_EFAIL;
  365. /* Save the suspend type */
  366. hdata->suspend_type = suspend_type;
  367. /*
  368. * Save context which will be restored after resuming from
  369. * non-retentive suspend.
  370. */
  371. if (suspend_type & SBI_HSM_SUSP_NON_RET_BIT)
  372. __sbi_hsm_suspend_non_ret_save(scratch);
  373. /* Try platform specific suspend */
  374. ret = hsm_device_hart_suspend(suspend_type);
  375. if (ret == SBI_ENOTSUPP) {
  376. /* Try generic implementation of default suspend types */
  377. if (suspend_type == SBI_HSM_SUSPEND_RET_DEFAULT ||
  378. suspend_type == SBI_HSM_SUSPEND_NON_RET_DEFAULT) {
  379. ret = __sbi_hsm_suspend_default(scratch);
  380. }
  381. }
  382. /*
  383. * The platform may have coordinated a retentive suspend, or it may
  384. * have exited early from a non-retentive suspend. Either way, the
  385. * caller is not expecting a successful return, so jump to the warm
  386. * boot entry point to simulate resume from a non-retentive suspend.
  387. */
  388. if (ret == 0 && (suspend_type & SBI_HSM_SUSP_NON_RET_BIT)) {
  389. void (*jump_warmboot)(void) =
  390. (void (*)(void))scratch->warmboot_addr;
  391. jump_warmboot();
  392. }
  393. /*
  394. * We might have successfully resumed from retentive suspend
  395. * or suspend failed. In both cases, we restore state of hart.
  396. */
  397. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_SUSPENDED,
  398. SBI_HSM_STATE_STARTED))
  399. sbi_hart_hang();
  400. return ret;
  401. }