plic.c 3.9 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. * Samuel Holland <samuel@sholland.org>
  9. */
  10. #include <sbi/riscv_io.h>
  11. #include <sbi/riscv_encoding.h>
  12. #include <sbi/sbi_console.h>
  13. #include <sbi/sbi_error.h>
  14. #include <sbi/sbi_string.h>
  15. #include <sbi_utils/irqchip/plic.h>
  16. #define PLIC_PRIORITY_BASE 0x0
  17. #define PLIC_PENDING_BASE 0x1000
  18. #define PLIC_ENABLE_BASE 0x2000
  19. #define PLIC_ENABLE_STRIDE 0x80
  20. #define PLIC_CONTEXT_BASE 0x200000
  21. #define PLIC_CONTEXT_STRIDE 0x1000
  22. static u32 plic_get_priority(const struct plic_data *plic, u32 source)
  23. {
  24. volatile void *plic_priority = (char *)plic->addr +
  25. PLIC_PRIORITY_BASE + 4 * source;
  26. return readl(plic_priority);
  27. }
  28. static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
  29. {
  30. volatile void *plic_priority = (char *)plic->addr +
  31. PLIC_PRIORITY_BASE + 4 * source;
  32. writel(val, plic_priority);
  33. }
  34. void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
  35. {
  36. for (u32 i = 1; i <= num; i++)
  37. priority[i] = plic_get_priority(plic, i);
  38. }
  39. void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
  40. u32 num)
  41. {
  42. for (u32 i = 1; i <= num; i++)
  43. plic_set_priority(plic, i, priority[i]);
  44. }
  45. static u32 plic_get_thresh(const struct plic_data *plic, u32 cntxid)
  46. {
  47. volatile void *plic_thresh;
  48. plic_thresh = (char *)plic->addr +
  49. PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
  50. return readl(plic_thresh);
  51. }
  52. static void plic_set_thresh(const struct plic_data *plic, u32 cntxid, u32 val)
  53. {
  54. volatile void *plic_thresh;
  55. plic_thresh = (char *)plic->addr +
  56. PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
  57. writel(val, plic_thresh);
  58. }
  59. static u32 plic_get_ie(const struct plic_data *plic, u32 cntxid,
  60. u32 word_index)
  61. {
  62. volatile void *plic_ie;
  63. plic_ie = (char *)plic->addr +
  64. PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid +
  65. 4 * word_index;
  66. return readl(plic_ie);
  67. }
  68. static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
  69. u32 word_index, u32 val)
  70. {
  71. volatile void *plic_ie;
  72. plic_ie = (char *)plic->addr +
  73. PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid +
  74. 4 * word_index;
  75. writel(val, plic_ie);
  76. }
  77. void plic_context_save(const struct plic_data *plic, int context_id,
  78. u32 *enable, u32 *threshold)
  79. {
  80. u32 ie_words = (plic->num_src + 31) / 32;
  81. for (u32 i = 0; i < ie_words; i++)
  82. enable[i] = plic_get_ie(plic, context_id, i);
  83. *threshold = plic_get_thresh(plic, context_id);
  84. }
  85. void plic_context_restore(const struct plic_data *plic, int context_id,
  86. const u32 *enable, u32 threshold)
  87. {
  88. u32 ie_words = (plic->num_src + 31) / 32;
  89. for (u32 i = 0; i < ie_words; i++)
  90. plic_set_ie(plic, context_id, i, enable[i]);
  91. plic_set_thresh(plic, context_id, threshold);
  92. }
  93. int plic_context_init(const struct plic_data *plic, int context_id,
  94. bool enable, u32 threshold)
  95. {
  96. u32 ie_words, ie_value;
  97. if (!plic || context_id < 0)
  98. return SBI_EINVAL;
  99. ie_words = plic->num_src / 32 + 1;
  100. ie_value = enable ? 0xffffffffU : 0U;
  101. for (u32 i = 0; i < ie_words; i++)
  102. plic_set_ie(plic, context_id, i, ie_value);
  103. plic_set_thresh(plic, context_id, threshold);
  104. return 0;
  105. }
  106. int plic_warm_irqchip_init(const struct plic_data *plic,
  107. int m_cntx_id, int s_cntx_id)
  108. {
  109. int ret;
  110. /* By default, disable all IRQs for M-mode of target HART */
  111. if (m_cntx_id > -1) {
  112. ret = plic_context_init(plic, m_cntx_id, false, 0x7);
  113. if (ret)
  114. return ret;
  115. }
  116. /* By default, disable all IRQs for S-mode of target HART */
  117. if (s_cntx_id > -1) {
  118. ret = plic_context_init(plic, s_cntx_id, false, 0x7);
  119. if (ret)
  120. return ret;
  121. }
  122. return 0;
  123. }
  124. int plic_cold_irqchip_init(const struct plic_data *plic)
  125. {
  126. int i;
  127. if (!plic)
  128. return SBI_EINVAL;
  129. /* Configure default priorities of all IRQs */
  130. for (i = 1; i <= plic->num_src; i++)
  131. plic_set_priority(plic, i, 0);
  132. return 0;
  133. }