sbi_hsm.c 13 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2020 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_barrier.h>
  11. #include <sbi/riscv_encoding.h>
  12. #include <sbi/riscv_atomic.h>
  13. #include <sbi/sbi_bitops.h>
  14. #include <sbi/sbi_console.h>
  15. #include <sbi/sbi_domain.h>
  16. #include <sbi/sbi_error.h>
  17. #include <sbi/sbi_ecall_interface.h>
  18. #include <sbi/sbi_hart.h>
  19. #include <sbi/sbi_hartmask.h>
  20. #include <sbi/sbi_hsm.h>
  21. #include <sbi/sbi_init.h>
  22. #include <sbi/sbi_ipi.h>
  23. #include <sbi/sbi_scratch.h>
  24. #include <sbi/sbi_system.h>
  25. #include <sbi/sbi_timer.h>
  26. #include <sbi/sbi_console.h>
  27. #define __sbi_hsm_hart_change_state(hdata, oldstate, newstate) \
  28. ({ \
  29. long state = atomic_cmpxchg(&(hdata)->state, oldstate, newstate); \
  30. if (state != (oldstate)) \
  31. sbi_printf("%s: ERR: The hart is in invalid state [%lu]\n", \
  32. __func__, state); \
  33. state == (oldstate); \
  34. })
  35. static const struct sbi_hsm_device *hsm_dev = NULL;
  36. static unsigned long hart_data_offset;
  37. /** Per hart specific data to manage state transition **/
  38. struct sbi_hsm_data {
  39. atomic_t state;
  40. unsigned long suspend_type;
  41. unsigned long saved_mie;
  42. unsigned long saved_mip;
  43. };
  44. bool sbi_hsm_hart_change_state(struct sbi_scratch *scratch, long oldstate,
  45. long newstate)
  46. {
  47. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  48. hart_data_offset);
  49. return __sbi_hsm_hart_change_state(hdata, oldstate, newstate);
  50. }
  51. int __sbi_hsm_hart_get_state(u32 hartid)
  52. {
  53. struct sbi_hsm_data *hdata;
  54. struct sbi_scratch *scratch;
  55. scratch = sbi_hartid_to_scratch(hartid);
  56. if (!scratch)
  57. return SBI_EINVAL;
  58. hdata = sbi_scratch_offset_ptr(scratch, hart_data_offset);
  59. return atomic_read(&hdata->state);
  60. }
  61. int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid)
  62. {
  63. if (!sbi_domain_is_assigned_hart(dom, hartid))
  64. return SBI_EINVAL;
  65. return __sbi_hsm_hart_get_state(hartid);
  66. }
  67. /**
  68. * Get ulong HART mask for given HART base ID
  69. * @param dom the domain to be used for output HART mask
  70. * @param hbase the HART base ID
  71. * @param out_hmask the output ulong HART mask
  72. * @return 0 on success and SBI_Exxx (< 0) on failure
  73. * Note: the output HART mask will be set to zero on failure as well.
  74. */
  75. int sbi_hsm_hart_interruptible_mask(const struct sbi_domain *dom,
  76. ulong hbase, ulong *out_hmask)
  77. {
  78. int hstate;
  79. ulong i, hmask, dmask;
  80. ulong hend = sbi_scratch_last_hartid() + 1;
  81. *out_hmask = 0;
  82. if (hend <= hbase)
  83. return SBI_EINVAL;
  84. if (BITS_PER_LONG < (hend - hbase))
  85. hend = hbase + BITS_PER_LONG;
  86. dmask = sbi_domain_get_assigned_hartmask(dom, hbase);
  87. for (i = hbase; i < hend; i++) {
  88. hmask = 1UL << (i - hbase);
  89. if (dmask & hmask) {
  90. hstate = __sbi_hsm_hart_get_state(i);
  91. if (hstate == SBI_HSM_STATE_STARTED ||
  92. hstate == SBI_HSM_STATE_SUSPENDED)
  93. *out_hmask |= hmask;
  94. }
  95. }
  96. return 0;
  97. }
  98. void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid)
  99. {
  100. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  101. hart_data_offset);
  102. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_START_PENDING,
  103. SBI_HSM_STATE_STARTED))
  104. sbi_hart_hang();
  105. }
  106. static void sbi_hsm_hart_wait(struct sbi_scratch *scratch, u32 hartid)
  107. {
  108. unsigned long saved_mie;
  109. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  110. hart_data_offset);
  111. /* Save MIE CSR */
  112. saved_mie = csr_read(CSR_MIE);
  113. /* Set MSIE and MEIE bits to receive IPI */
  114. csr_set(CSR_MIE, MIP_MSIP | MIP_MEIP);
  115. /* Wait for state transition requested by sbi_hsm_hart_start() */
  116. while (atomic_read(&hdata->state) != SBI_HSM_STATE_START_PENDING) {
  117. wfi();
  118. };
  119. /* Restore MIE CSR */
  120. csr_write(CSR_MIE, saved_mie);
  121. /*
  122. * No need to clear IPI here because the sbi_ipi_init() will
  123. * clear it for current HART via sbi_platform_ipi_init().
  124. */
  125. }
  126. const struct sbi_hsm_device *sbi_hsm_get_device(void)
  127. {
  128. return hsm_dev;
  129. }
  130. void sbi_hsm_set_device(const struct sbi_hsm_device *dev)
  131. {
  132. if (!dev || hsm_dev)
  133. return;
  134. hsm_dev = dev;
  135. }
  136. static bool hsm_device_has_hart_hotplug(void)
  137. {
  138. if (hsm_dev && hsm_dev->hart_start && hsm_dev->hart_stop)
  139. return true;
  140. return false;
  141. }
  142. static bool hsm_device_has_hart_secondary_boot(void)
  143. {
  144. if (hsm_dev && hsm_dev->hart_start && !hsm_dev->hart_stop)
  145. return true;
  146. return false;
  147. }
  148. static int hsm_device_hart_start(u32 hartid, ulong saddr)
  149. {
  150. if (hsm_dev && hsm_dev->hart_start)
  151. return hsm_dev->hart_start(hartid, saddr);
  152. return SBI_ENOTSUPP;
  153. }
  154. static int hsm_device_hart_stop(void)
  155. {
  156. if (hsm_dev && hsm_dev->hart_stop)
  157. return hsm_dev->hart_stop();
  158. return SBI_ENOTSUPP;
  159. }
  160. static int hsm_device_hart_suspend(u32 suspend_type)
  161. {
  162. if (hsm_dev && hsm_dev->hart_suspend)
  163. return hsm_dev->hart_suspend(suspend_type);
  164. return SBI_ENOTSUPP;
  165. }
  166. static void hsm_device_hart_resume(void)
  167. {
  168. if (hsm_dev && hsm_dev->hart_resume)
  169. hsm_dev->hart_resume();
  170. }
  171. int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
  172. {
  173. u32 i;
  174. struct sbi_scratch *rscratch;
  175. struct sbi_hsm_data *hdata;
  176. if (cold_boot) {
  177. hart_data_offset = sbi_scratch_alloc_offset(sizeof(*hdata));
  178. if (!hart_data_offset)
  179. return SBI_ENOMEM;
  180. /* Initialize hart state data for every hart */
  181. for (i = 0; i <= sbi_scratch_last_hartid(); i++) {
  182. rscratch = sbi_hartid_to_scratch(i);
  183. if (!rscratch)
  184. continue;
  185. hdata = sbi_scratch_offset_ptr(rscratch,
  186. hart_data_offset);
  187. ATOMIC_INIT(&hdata->state,
  188. (i == hartid) ?
  189. SBI_HSM_STATE_START_PENDING :
  190. SBI_HSM_STATE_STOPPED);
  191. }
  192. } else {
  193. sbi_hsm_hart_wait(scratch, hartid);
  194. }
  195. return 0;
  196. }
  197. void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch)
  198. {
  199. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  200. hart_data_offset);
  201. void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;
  202. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_STOP_PENDING,
  203. SBI_HSM_STATE_STOPPED))
  204. goto fail_exit;
  205. if (hsm_device_has_hart_hotplug()) {
  206. if (hsm_device_hart_stop() != SBI_ENOTSUPP)
  207. goto fail_exit;
  208. }
  209. /**
  210. * As platform is lacking support for hotplug, directly jump to warmboot
  211. * and wait for interrupts in warmboot. We do it preemptively in order
  212. * preserve the hart states and reuse the code path for hotplug.
  213. */
  214. jump_warmboot();
  215. fail_exit:
  216. /* It should never reach here */
  217. sbi_printf("ERR: Failed stop hart [%u]\n", current_hartid());
  218. sbi_hart_hang();
  219. }
  220. int sbi_hsm_hart_start(struct sbi_scratch *scratch,
  221. const struct sbi_domain *dom,
  222. u32 hartid, ulong saddr, ulong smode, ulong arg1)
  223. {
  224. unsigned long init_count;
  225. unsigned int hstate;
  226. struct sbi_scratch *rscratch;
  227. struct sbi_hsm_data *hdata;
  228. /* For now, we only allow start mode to be S-mode or U-mode. */
  229. if (smode != PRV_S && smode != PRV_U)
  230. return SBI_EINVAL;
  231. if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
  232. return SBI_EINVAL;
  233. if (dom && !sbi_domain_check_addr(dom, saddr, smode,
  234. SBI_DOMAIN_EXECUTE))
  235. return SBI_EINVALID_ADDR;
  236. rscratch = sbi_hartid_to_scratch(hartid);
  237. if (!rscratch)
  238. return SBI_EINVAL;
  239. hdata = sbi_scratch_offset_ptr(rscratch, hart_data_offset);
  240. hstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_STOPPED,
  241. SBI_HSM_STATE_START_PENDING);
  242. if (hstate == SBI_HSM_STATE_STARTED)
  243. return SBI_EALREADY;
  244. /**
  245. * if a hart is already transition to start or stop, another start call
  246. * is considered as invalid request.
  247. */
  248. if (hstate != SBI_HSM_STATE_STOPPED)
  249. return SBI_EINVAL;
  250. init_count = sbi_init_count(hartid);
  251. rscratch->next_arg1 = arg1;
  252. rscratch->next_addr = saddr;
  253. rscratch->next_mode = smode;
  254. if (hsm_device_has_hart_hotplug() ||
  255. (hsm_device_has_hart_secondary_boot() && !init_count)) {
  256. return hsm_device_hart_start(hartid, scratch->warmboot_addr);
  257. } else {
  258. int rc = sbi_ipi_raw_send(hartid);
  259. if (rc)
  260. return rc;
  261. }
  262. return 0;
  263. }
  264. int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow)
  265. {
  266. const struct sbi_domain *dom = sbi_domain_thishart_ptr();
  267. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  268. hart_data_offset);
  269. if (!dom)
  270. return SBI_EFAIL;
  271. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_STARTED,
  272. SBI_HSM_STATE_STOP_PENDING))
  273. return SBI_EFAIL;
  274. if (exitnow)
  275. sbi_exit(scratch);
  276. return 0;
  277. }
  278. static int __sbi_hsm_suspend_default(struct sbi_scratch *scratch)
  279. {
  280. /* Wait for interrupt */
  281. wfi();
  282. return 0;
  283. }
  284. void __sbi_hsm_suspend_non_ret_save(struct sbi_scratch *scratch)
  285. {
  286. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  287. hart_data_offset);
  288. /*
  289. * We will be resuming in warm-boot path so the MIE and MIP CSRs
  290. * will be back to initial state. It is possible that HART has
  291. * configured timer event before going to suspend state so we
  292. * should save MIE and MIP CSRs and restore it after resuming.
  293. *
  294. * Further, the M-mode bits in MIP CSR are read-only and set by
  295. * external devices (such as interrupt controller) whereas all
  296. * VS-mode bits in MIP are read-only alias of bits in HVIP CSR.
  297. *
  298. * This means we should only save/restore S-mode bits of MIP CSR
  299. * such as MIP.SSIP and MIP.STIP.
  300. */
  301. hdata->saved_mie = csr_read(CSR_MIE);
  302. hdata->saved_mip = csr_read(CSR_MIP) & (MIP_SSIP | MIP_STIP);
  303. }
  304. static void __sbi_hsm_suspend_non_ret_restore(struct sbi_scratch *scratch)
  305. {
  306. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  307. hart_data_offset);
  308. csr_write(CSR_MIE, hdata->saved_mie);
  309. csr_set(CSR_MIP, (hdata->saved_mip & (MIP_SSIP | MIP_STIP)));
  310. }
  311. void sbi_hsm_hart_resume_start(struct sbi_scratch *scratch)
  312. {
  313. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  314. hart_data_offset);
  315. /* If current HART was SUSPENDED then set RESUME_PENDING state */
  316. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_SUSPENDED,
  317. SBI_HSM_STATE_RESUME_PENDING))
  318. sbi_hart_hang();
  319. hsm_device_hart_resume();
  320. }
  321. void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch)
  322. {
  323. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  324. hart_data_offset);
  325. /* If current HART was RESUME_PENDING then set STARTED state */
  326. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_RESUME_PENDING,
  327. SBI_HSM_STATE_STARTED))
  328. sbi_hart_hang();
  329. /*
  330. * Restore some of the M-mode CSRs which we are re-configured by
  331. * the warm-boot sequence.
  332. */
  333. __sbi_hsm_suspend_non_ret_restore(scratch);
  334. }
  335. int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
  336. ulong raddr, ulong rmode, ulong arg1)
  337. {
  338. int ret;
  339. const struct sbi_domain *dom = sbi_domain_thishart_ptr();
  340. struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
  341. hart_data_offset);
  342. /* Sanity check on domain assigned to current HART */
  343. if (!dom)
  344. return SBI_EFAIL;
  345. /* Sanity check on suspend type */
  346. if (SBI_HSM_SUSPEND_RET_DEFAULT < suspend_type &&
  347. suspend_type < SBI_HSM_SUSPEND_RET_PLATFORM)
  348. return SBI_EINVAL;
  349. if (SBI_HSM_SUSPEND_NON_RET_DEFAULT < suspend_type &&
  350. suspend_type < SBI_HSM_SUSPEND_NON_RET_PLATFORM)
  351. return SBI_EINVAL;
  352. /* Additional sanity check for non-retentive suspend */
  353. if (suspend_type & SBI_HSM_SUSP_NON_RET_BIT) {
  354. /*
  355. * For now, we only allow non-retentive suspend from
  356. * S-mode or U-mode.
  357. */
  358. if (rmode != PRV_S && rmode != PRV_U)
  359. return SBI_EFAIL;
  360. if (dom && !sbi_domain_check_addr(dom, raddr, rmode,
  361. SBI_DOMAIN_EXECUTE))
  362. return SBI_EINVALID_ADDR;
  363. }
  364. /* Save the resume address and resume mode */
  365. scratch->next_arg1 = arg1;
  366. scratch->next_addr = raddr;
  367. scratch->next_mode = rmode;
  368. /* Directly move from STARTED to SUSPENDED state */
  369. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_STARTED,
  370. SBI_HSM_STATE_SUSPENDED))
  371. return SBI_EFAIL;
  372. /* Save the suspend type */
  373. hdata->suspend_type = suspend_type;
  374. /*
  375. * Save context which will be restored after resuming from
  376. * non-retentive suspend.
  377. */
  378. if (suspend_type & SBI_HSM_SUSP_NON_RET_BIT)
  379. __sbi_hsm_suspend_non_ret_save(scratch);
  380. /* Try platform specific suspend */
  381. ret = hsm_device_hart_suspend(suspend_type);
  382. if (ret == SBI_ENOTSUPP) {
  383. /* Try generic implementation of default suspend types */
  384. if (suspend_type == SBI_HSM_SUSPEND_RET_DEFAULT ||
  385. suspend_type == SBI_HSM_SUSPEND_NON_RET_DEFAULT) {
  386. ret = __sbi_hsm_suspend_default(scratch);
  387. }
  388. }
  389. /*
  390. * The platform may have coordinated a retentive suspend, or it may
  391. * have exited early from a non-retentive suspend. Either way, the
  392. * caller is not expecting a successful return, so jump to the warm
  393. * boot entry point to simulate resume from a non-retentive suspend.
  394. */
  395. if (ret == 0 && (suspend_type & SBI_HSM_SUSP_NON_RET_BIT)) {
  396. void (*jump_warmboot)(void) =
  397. (void (*)(void))scratch->warmboot_addr;
  398. jump_warmboot();
  399. }
  400. /*
  401. * We might have successfully resumed from retentive suspend
  402. * or suspend failed. In both cases, we restore state of hart.
  403. */
  404. if (!__sbi_hsm_hart_change_state(hdata, SBI_HSM_STATE_SUSPENDED,
  405. SBI_HSM_STATE_STARTED))
  406. sbi_hart_hang();
  407. return ret;
  408. }