sbi_trap.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191
  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_encoding.h>
  11. #include <sbi/sbi_console.h>
  12. #include <sbi/sbi_ecall.h>
  13. #include <sbi/sbi_error.h>
  14. #include <sbi/sbi_hart.h>
  15. #include <sbi/sbi_illegal_insn.h>
  16. #include <sbi/sbi_ipi.h>
  17. #include <sbi/sbi_misaligned_ldst.h>
  18. #include <sbi/sbi_timer.h>
  19. #include <sbi/sbi_trap.h>
  20. static void __noreturn sbi_trap_error(const char *msg,
  21. int rc, u32 hartid,
  22. ulong mcause, ulong mtval,
  23. struct sbi_trap_regs *regs)
  24. {
  25. sbi_printf("%s: hart%d: %s (error %d)\n",
  26. __func__, hartid, msg, rc);
  27. sbi_printf("%s: hart%d: mcause=0x%"PRILX" mtval=0x%"PRILX"\n",
  28. __func__, hartid, mcause, mtval);
  29. sbi_printf("%s: hart%d: mepc=0x%"PRILX" mstatus=0x%"PRILX"\n",
  30. __func__, hartid, regs->mepc, regs->mstatus);
  31. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  32. __func__, hartid, "ra", regs->ra, "sp", regs->sp);
  33. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  34. __func__, hartid, "gp", regs->gp, "tp", regs->tp);
  35. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  36. __func__, hartid, "s0", regs->s0, "s1", regs->s1);
  37. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  38. __func__, hartid, "a0", regs->a0, "a1", regs->a1);
  39. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  40. __func__, hartid, "a2", regs->a2, "a3", regs->a3);
  41. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  42. __func__, hartid, "a4", regs->a4, "a5", regs->a5);
  43. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  44. __func__, hartid, "a6", regs->a6, "a7", regs->a7);
  45. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  46. __func__, hartid, "s2", regs->s2, "s3", regs->s3);
  47. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  48. __func__, hartid, "s4", regs->s4, "s5", regs->s5);
  49. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  50. __func__, hartid, "s6", regs->s6, "s7", regs->s7);
  51. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  52. __func__, hartid, "s8", regs->s8, "s9", regs->s9);
  53. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  54. __func__, hartid, "s10", regs->s10, "s11", regs->s11);
  55. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  56. __func__, hartid, "t0", regs->t0, "t1", regs->t1);
  57. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  58. __func__, hartid, "t2", regs->t2, "t3", regs->t3);
  59. sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
  60. __func__, hartid, "t4", regs->t4, "t5", regs->t5);
  61. sbi_printf("%s: hart%d: %s=0x%"PRILX"\n",
  62. __func__, hartid, "t6", regs->t6);
  63. sbi_hart_hang();
  64. }
  65. /**
  66. * Redirect trap to lower privledge mode (S-mode or U-mode)
  67. *
  68. * @param regs pointer to register state
  69. * @param scratch pointer to sbi_scratch of current HART
  70. * @param epc error PC for lower privledge mode
  71. * @param cause exception cause for lower privledge mode
  72. * @param tval trap value for lower privledge mode
  73. *
  74. * @return 0 on success and negative error code on failure
  75. */
  76. int sbi_trap_redirect(struct sbi_trap_regs *regs,
  77. struct sbi_scratch *scratch,
  78. ulong epc, ulong cause, ulong tval)
  79. {
  80. ulong new_mstatus, prev_mode;
  81. /* Sanity check on previous mode */
  82. prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
  83. if (prev_mode != PRV_S && prev_mode != PRV_U)
  84. return SBI_ENOTSUPP;
  85. /* Update S-mode exception info */
  86. csr_write(CSR_STVAL, tval);
  87. csr_write(CSR_SEPC, epc);
  88. csr_write(CSR_SCAUSE, cause);
  89. /* Set MEPC to S-mode exception vector base */
  90. regs->mepc = csr_read(CSR_STVEC);
  91. /* Initial value of new MSTATUS */
  92. new_mstatus = regs->mstatus;
  93. /* Clear MPP, SPP, SPIE, and SIE */
  94. new_mstatus &= ~(MSTATUS_MPP |
  95. MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE);
  96. /* Set SPP */
  97. if (prev_mode == PRV_S)
  98. new_mstatus |= (1UL << MSTATUS_SPP_SHIFT);
  99. /* Set SPIE */
  100. if (regs->mstatus & MSTATUS_SIE)
  101. new_mstatus |= (1UL << MSTATUS_SPIE_SHIFT);
  102. /* Set MPP */
  103. new_mstatus |= (PRV_S << MSTATUS_MPP_SHIFT);
  104. /* Set new value in MSTATUS */
  105. regs->mstatus = new_mstatus;
  106. return 0;
  107. }
  108. /**
  109. * Handle trap/interrupt
  110. *
  111. * This function is called by firmware linked to OpenSBI
  112. * library for handling trap/interrupt. It expects the
  113. * following:
  114. * 1. The 'mscratch' CSR is pointing to sbi_scratch of current HART
  115. * 2. The 'mcause' CSR is having exception/interrupt cause
  116. * 3. The 'mtval' CSR is having additional trap information
  117. * 4. Stack pointer (SP) is setup for current HART
  118. * 5. Interrupts are disabled in MSTATUS CSR
  119. *
  120. * @param regs pointer to register state
  121. * @param scratch pointer to sbi_scratch of current HART
  122. */
  123. void sbi_trap_handler(struct sbi_trap_regs *regs,
  124. struct sbi_scratch *scratch)
  125. {
  126. int rc = SBI_ENOTSUPP;
  127. const char *msg = "trap handler failed";
  128. u32 hartid = sbi_current_hartid();
  129. ulong mcause = csr_read(CSR_MCAUSE);
  130. ulong mtval = csr_read(CSR_MTVAL);
  131. if (mcause & (1UL << (__riscv_xlen - 1))) {
  132. mcause &= ~(1UL << (__riscv_xlen - 1));
  133. switch (mcause) {
  134. case IRQ_M_TIMER:
  135. sbi_timer_process(scratch);
  136. break;
  137. case IRQ_M_SOFT:
  138. sbi_ipi_process(scratch);
  139. break;
  140. default:
  141. msg = "unhandled external interrupt";
  142. goto trap_error;
  143. };
  144. return;
  145. }
  146. switch (mcause) {
  147. case CAUSE_ILLEGAL_INSTRUCTION:
  148. rc = sbi_illegal_insn_handler(hartid, mcause, regs, scratch);
  149. msg = "illegal instruction handler failed";
  150. break;
  151. case CAUSE_MISALIGNED_LOAD:
  152. rc = sbi_misaligned_load_handler(hartid, mcause, regs, scratch);
  153. msg = "misaligned load handler failed";
  154. break;
  155. case CAUSE_MISALIGNED_STORE:
  156. rc = sbi_misaligned_store_handler(hartid, mcause, regs, scratch);
  157. msg = "misaligned store handler failed";
  158. break;
  159. case CAUSE_SUPERVISOR_ECALL:
  160. case CAUSE_HYPERVISOR_ECALL:
  161. rc = sbi_ecall_handler(hartid, mcause, regs, scratch);
  162. msg = "ecall handler failed";
  163. break;
  164. default:
  165. /* If the trap came from S or U mode, redirect it there */
  166. rc = sbi_trap_redirect(regs, scratch, regs->mepc, mcause, mtval);
  167. break;
  168. };
  169. trap_error:
  170. if (rc) {
  171. sbi_trap_error(msg, rc, hartid, mcause, csr_read(CSR_MTVAL), regs);
  172. }
  173. }