sbi_pmu.c 20 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/sbi_bitops.h>
  11. #include <sbi/sbi_console.h>
  12. #include <sbi/sbi_hart.h>
  13. #include <sbi/sbi_platform.h>
  14. #include <sbi/sbi_pmu.h>
  15. #include <sbi/sbi_scratch.h>
  16. #include <sbi/sbi_string.h>
  17. /** Information about hardware counters */
  18. struct sbi_pmu_hw_event {
  19. uint32_t counters;
  20. uint32_t start_idx;
  21. uint32_t end_idx;
  22. /* Event selector value used only for raw events */
  23. uint64_t select;
  24. };
  25. /** Representation of a firmware event */
  26. struct sbi_pmu_fw_event {
  27. /* Event associated with the particular counter */
  28. uint32_t event_idx;
  29. /* Current value of the counter */
  30. unsigned long curr_count;
  31. /* A flag indicating pmu event monitoring is started */
  32. bool bStarted;
  33. };
  34. /* Information about PMU counters as per SBI specification */
  35. union sbi_pmu_ctr_info {
  36. unsigned long value;
  37. struct {
  38. unsigned long csr:12;
  39. unsigned long width:6;
  40. #if __riscv_xlen == 32
  41. unsigned long reserved:13;
  42. #else
  43. unsigned long reserved:45;
  44. #endif
  45. unsigned long type:1;
  46. };
  47. };
  48. /* Mapping between event range and possible counters */
  49. static struct sbi_pmu_hw_event hw_event_map[SBI_PMU_HW_EVENT_MAX] = {0};
  50. /* counter to enabled event mapping */
  51. static uint32_t active_events[SBI_HARTMASK_MAX_BITS][SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX];
  52. /* Contains all the information about firmwares events */
  53. static struct sbi_pmu_fw_event fw_event_map[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_EVENT_MAX] = {0};
  54. /* Maximum number of hardware events available */
  55. static uint32_t num_hw_events;
  56. /* Maximum number of hardware counters available */
  57. static uint32_t num_hw_ctrs;
  58. /* Maximum number of counters available */
  59. static uint32_t total_ctrs;
  60. /* Helper macros to retrieve event idx and code type */
  61. #define get_cidx_type(x) ((x & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16)
  62. #define get_cidx_code(x) (x & SBI_PMU_EVENT_IDX_CODE_MASK)
  63. /**
  64. * Perform a sanity check on event & counter mappings with event range overlap check
  65. * @param evtA Pointer to the existing hw event structure
  66. * @param evtB Pointer to the new hw event structure
  67. *
  68. * Return FALSE if the range doesn't overlap, TRUE otherwise
  69. */
  70. static bool pmu_event_range_overlap(struct sbi_pmu_hw_event *evtA,
  71. struct sbi_pmu_hw_event *evtB)
  72. {
  73. /* check if the range of events overlap with a previous entry */
  74. if (((evtA->end_idx < evtB->start_idx) && (evtA->end_idx < evtB->end_idx)) ||
  75. ((evtA->start_idx > evtB->start_idx) && (evtA->start_idx > evtB->end_idx)))
  76. return FALSE;
  77. return TRUE;
  78. }
  79. static bool pmu_event_select_overlap(struct sbi_pmu_hw_event *evt,
  80. uint64_t select_val)
  81. {
  82. if (evt->select == select_val)
  83. return TRUE;
  84. return FALSE;
  85. }
  86. static int pmu_ctr_validate(uint32_t cidx, uint32_t *event_idx_code)
  87. {
  88. uint32_t event_idx_val;
  89. uint32_t event_idx_type;
  90. u32 hartid = current_hartid();
  91. event_idx_val = active_events[hartid][cidx];
  92. if (cidx >= total_ctrs || (event_idx_val == SBI_PMU_EVENT_IDX_INVALID))
  93. return SBI_EINVAL;
  94. event_idx_type = get_cidx_type(event_idx_val);
  95. if (event_idx_type >= SBI_PMU_EVENT_TYPE_MAX)
  96. return SBI_EINVAL;
  97. *event_idx_code = get_cidx_code(event_idx_val);
  98. return event_idx_type;
  99. }
  100. static int pmu_ctr_read_fw(uint32_t cidx, unsigned long *cval,
  101. uint32_t fw_evt_code)
  102. {
  103. u32 hartid = current_hartid();
  104. struct sbi_pmu_fw_event fevent;
  105. fevent = fw_event_map[hartid][fw_evt_code];
  106. *cval = fevent.curr_count;
  107. return 0;
  108. }
  109. /* Add a hardware counter read for completeness for future purpose */
  110. static int pmu_ctr_read_hw(uint32_t cidx, uint64_t *cval)
  111. {
  112. /* Check for invalid hw counter read requests */
  113. if (unlikely(cidx == 1))
  114. return SBI_EINVAL;
  115. #if __riscv_xlen == 32
  116. uint32_t temp, temph = 0;
  117. temp = csr_read_num(CSR_MCYCLE + cidx);
  118. temph = csr_read_num(CSR_MCYCLEH + cidx);
  119. *cval = ((uint64_t)temph << 32) | temp;
  120. #else
  121. *cval = csr_read_num(CSR_MCYCLE + cidx);
  122. #endif
  123. return 0;
  124. }
  125. int sbi_pmu_ctr_read(uint32_t cidx, unsigned long *cval)
  126. {
  127. int event_idx_type;
  128. uint32_t event_code;
  129. uint64_t cval64;
  130. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  131. if (event_idx_type < 0)
  132. return SBI_EINVAL;
  133. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
  134. pmu_ctr_read_fw(cidx, cval, event_code);
  135. else
  136. pmu_ctr_read_hw(cidx, &cval64);
  137. return 0;
  138. }
  139. static int pmu_add_hw_event_map(u32 eidx_start, u32 eidx_end, u32 cmap,
  140. uint64_t select)
  141. {
  142. int i = 0;
  143. bool is_overlap;
  144. struct sbi_pmu_hw_event *event = &hw_event_map[num_hw_events];
  145. /* The first two counters are reserved by priv spec */
  146. if (eidx_start > SBI_PMU_HW_INSTRUCTIONS && (cmap & SBI_PMU_FIXED_CTR_MASK))
  147. return SBI_EDENIED;
  148. if (num_hw_events >= SBI_PMU_HW_EVENT_MAX - 1) {
  149. sbi_printf("Can not handle more than %d perf events\n",
  150. SBI_PMU_HW_EVENT_MAX);
  151. return SBI_EFAIL;
  152. }
  153. event->start_idx = eidx_start;
  154. event->end_idx = eidx_end;
  155. /* Sanity check */
  156. for (i = 0; i < num_hw_events; i++) {
  157. if (eidx_start == SBI_PMU_EVENT_RAW_IDX)
  158. /* All raw events have same event idx. Just do sanity check on select */
  159. is_overlap = pmu_event_select_overlap(&hw_event_map[i], select);
  160. else
  161. is_overlap = pmu_event_range_overlap(&hw_event_map[i], event);
  162. if (is_overlap)
  163. goto reset_event;
  164. }
  165. event->counters = cmap;
  166. event->select = select;
  167. num_hw_events++;
  168. return 0;
  169. reset_event:
  170. event->start_idx = 0;
  171. event->end_idx = 0;
  172. return SBI_EINVAL;
  173. }
  174. /**
  175. * Logical counter ids are assigned to hardware counters are assigned consecutively.
  176. * E.g. counter0 must count MCYCLE where counter2 must count minstret. Similarly,
  177. * counterX will mhpmcounterX.
  178. */
  179. int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap)
  180. {
  181. if ((eidx_start > eidx_end) || eidx_start == SBI_PMU_EVENT_RAW_IDX ||
  182. eidx_end == SBI_PMU_EVENT_RAW_IDX)
  183. return SBI_EINVAL;
  184. return pmu_add_hw_event_map(eidx_start, eidx_end, cmap, 0);
  185. }
  186. int sbi_pmu_add_raw_event_counter_map(uint64_t select, u32 cmap)
  187. {
  188. return pmu_add_hw_event_map(SBI_PMU_EVENT_RAW_IDX,
  189. SBI_PMU_EVENT_RAW_IDX, cmap, select);
  190. }
  191. static int pmu_ctr_enable_irq_hw(int ctr_idx)
  192. {
  193. unsigned long mhpmevent_csr;
  194. unsigned long mhpmevent_curr;
  195. unsigned long mip_val;
  196. unsigned long of_mask;
  197. if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  198. return SBI_EFAIL;
  199. #if __riscv_xlen == 32
  200. mhpmevent_csr = CSR_MHPMEVENT3H + ctr_idx - 3;
  201. of_mask = ~MHPMEVENTH_OF;
  202. #else
  203. mhpmevent_csr = CSR_MHPMEVENT3 + ctr_idx - 3;
  204. of_mask = ~MHPMEVENT_OF;
  205. #endif
  206. mhpmevent_curr = csr_read_num(mhpmevent_csr);
  207. mip_val = csr_read(CSR_MIP);
  208. /**
  209. * Clear out the OF bit so that next interrupt can be enabled.
  210. * This should be done only when the corresponding overflow interrupt
  211. * bit is cleared. That indicates that software has already handled the
  212. * previous interrupts or the hardware yet to set an overflow interrupt.
  213. * Otherwise, there will be race conditions where we may clear the bit
  214. * the software is yet to handle the interrupt.
  215. */
  216. if (!(mip_val & MIP_LCOFIP)) {
  217. mhpmevent_curr &= of_mask;
  218. csr_write_num(mhpmevent_csr, mhpmevent_curr);
  219. }
  220. return 0;
  221. }
  222. static void pmu_ctr_write_hw(uint32_t cidx, uint64_t ival)
  223. {
  224. #if __riscv_xlen == 32
  225. csr_write_num(CSR_MCYCLE + cidx, 0);
  226. csr_write_num(CSR_MCYCLE + cidx, ival & 0xFFFFFFFF);
  227. csr_write_num(CSR_MCYCLEH + cidx, ival >> BITS_PER_LONG);
  228. #else
  229. csr_write_num(CSR_MCYCLE + cidx, ival);
  230. #endif
  231. }
  232. static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
  233. {
  234. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  235. unsigned long mctr_inhbt;
  236. /* Make sure the counter index lies within the range and is not TM bit */
  237. if (cidx > num_hw_ctrs || cidx == 1)
  238. return SBI_EINVAL;
  239. if (!sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT))
  240. goto skip_inhibit_update;
  241. /*
  242. * Some of the hardware may not support mcountinhibit but perf stat
  243. * still can work if supervisor mode programs the initial value.
  244. */
  245. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  246. if (!__test_bit(cidx, &mctr_inhbt))
  247. return SBI_EALREADY_STARTED;
  248. __clear_bit(cidx, &mctr_inhbt);
  249. if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SSCOFPMF))
  250. pmu_ctr_enable_irq_hw(cidx);
  251. csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt);
  252. skip_inhibit_update:
  253. if (ival_update)
  254. pmu_ctr_write_hw(cidx, ival);
  255. return 0;
  256. }
  257. static int pmu_ctr_start_fw(uint32_t cidx, uint32_t fw_evt_code,
  258. uint64_t ival, bool ival_update)
  259. {
  260. u32 hartid = current_hartid();
  261. struct sbi_pmu_fw_event *fevent;
  262. fevent = &fw_event_map[hartid][fw_evt_code];
  263. if (ival_update)
  264. fevent->curr_count = ival;
  265. fevent->bStarted = TRUE;
  266. return 0;
  267. }
  268. int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask,
  269. unsigned long flags, uint64_t ival)
  270. {
  271. int event_idx_type;
  272. uint32_t event_code;
  273. unsigned long ctr_mask = cmask << cbase;
  274. int ret = SBI_EINVAL;
  275. bool bUpdate = FALSE;
  276. if (__fls(ctr_mask) >= total_ctrs)
  277. return ret;
  278. if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE)
  279. bUpdate = TRUE;
  280. for_each_set_bit_from(cbase, &ctr_mask, total_ctrs) {
  281. event_idx_type = pmu_ctr_validate(cbase, &event_code);
  282. if (event_idx_type < 0)
  283. /* Continue the start operation for other counters */
  284. continue;
  285. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
  286. ret = pmu_ctr_start_fw(cbase, event_code, ival, bUpdate);
  287. else
  288. ret = pmu_ctr_start_hw(cbase, ival, bUpdate);
  289. }
  290. return ret;
  291. }
  292. static int pmu_ctr_stop_hw(uint32_t cidx)
  293. {
  294. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  295. unsigned long mctr_inhbt;
  296. if (!sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT))
  297. return 0;
  298. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  299. /* Make sure the counter index lies within the range and is not TM bit */
  300. if (cidx > num_hw_ctrs || cidx == 1)
  301. return SBI_EINVAL;
  302. if (!__test_bit(cidx, &mctr_inhbt)) {
  303. __set_bit(cidx, &mctr_inhbt);
  304. csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt);
  305. return 0;
  306. } else
  307. return SBI_EALREADY_STOPPED;
  308. }
  309. static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t fw_evt_code)
  310. {
  311. u32 hartid = current_hartid();
  312. fw_event_map[hartid][fw_evt_code].bStarted = FALSE;
  313. return 0;
  314. }
  315. static int pmu_reset_hw_mhpmevent(int ctr_idx)
  316. {
  317. if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  318. return SBI_EFAIL;
  319. #if __riscv_xlen == 32
  320. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0);
  321. csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, 0);
  322. #else
  323. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0);
  324. #endif
  325. return 0;
  326. }
  327. int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask,
  328. unsigned long flag)
  329. {
  330. u32 hartid = current_hartid();
  331. int ret = SBI_EINVAL;
  332. int event_idx_type;
  333. uint32_t event_code;
  334. unsigned long ctr_mask = cmask << cbase;
  335. if (__fls(ctr_mask) >= total_ctrs)
  336. return SBI_EINVAL;
  337. for_each_set_bit_from(cbase, &ctr_mask, total_ctrs) {
  338. event_idx_type = pmu_ctr_validate(cbase, &event_code);
  339. if (event_idx_type < 0)
  340. /* Continue the stop operation for other counters */
  341. continue;
  342. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
  343. ret = pmu_ctr_stop_fw(cbase, event_code);
  344. else
  345. ret = pmu_ctr_stop_hw(cbase);
  346. if (flag & SBI_PMU_STOP_FLAG_RESET) {
  347. active_events[hartid][cbase] = SBI_PMU_EVENT_IDX_INVALID;
  348. pmu_reset_hw_mhpmevent(cbase);
  349. }
  350. }
  351. return ret;
  352. }
  353. static void pmu_update_inhibit_flags(unsigned long flags, uint64_t *mhpmevent_val)
  354. {
  355. if (flags & SBI_PMU_CFG_FLAG_SET_VUINH)
  356. *mhpmevent_val |= MHPMEVENT_VUINH;
  357. if (flags & SBI_PMU_CFG_FLAG_SET_VSINH)
  358. *mhpmevent_val |= MHPMEVENT_VSINH;
  359. if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
  360. *mhpmevent_val |= MHPMEVENT_UINH;
  361. if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
  362. *mhpmevent_val |= MHPMEVENT_SINH;
  363. }
  364. static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
  365. unsigned long flags, unsigned long eindex,
  366. uint64_t data)
  367. {
  368. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  369. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  370. uint64_t mhpmevent_val;
  371. /* Get the final mhpmevent value to be written from platform */
  372. mhpmevent_val = sbi_platform_pmu_xlate_to_mhpmevent(plat, eindex, data);
  373. if (!mhpmevent_val || ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  374. return SBI_EFAIL;
  375. /* Always clear the OVF bit and inhibit countin of events in M-mode */
  376. mhpmevent_val = (mhpmevent_val & ~MHPMEVENT_SSCOF_MASK) | MHPMEVENT_MINH;
  377. /* Update the inhibit flags based on inhibit flags received from supervisor */
  378. pmu_update_inhibit_flags(flags, &mhpmevent_val);
  379. #if __riscv_xlen == 32
  380. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
  381. csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, mhpmevent_val >> BITS_PER_LONG);
  382. #else
  383. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val);
  384. #endif
  385. return 0;
  386. }
  387. static int pmu_ctr_find_fixed_fw(unsigned long evt_idx_code)
  388. {
  389. /* Non-programmables counters are enabled always. No need to do lookup */
  390. if (evt_idx_code == SBI_PMU_HW_CPU_CYCLES)
  391. return 0;
  392. else if (evt_idx_code == SBI_PMU_HW_INSTRUCTIONS)
  393. return 2;
  394. else
  395. return SBI_EINVAL;
  396. }
  397. static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned long flags,
  398. unsigned long event_idx, uint64_t data)
  399. {
  400. unsigned long ctr_mask;
  401. int i, ret = 0, fixed_ctr, ctr_idx = SBI_ENOTSUPP;
  402. struct sbi_pmu_hw_event *temp;
  403. unsigned long mctr_inhbt = 0;
  404. u32 hartid = current_hartid();
  405. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  406. if (cbase > num_hw_ctrs)
  407. return SBI_EINVAL;
  408. /**
  409. * If Sscof is present try to find the programmable counter for
  410. * cycle/instret as well.
  411. */
  412. fixed_ctr = pmu_ctr_find_fixed_fw(event_idx);
  413. if (fixed_ctr >= 0 &&
  414. !sbi_hart_has_feature(scratch, SBI_HART_HAS_SSCOFPMF))
  415. return fixed_ctr;
  416. if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT))
  417. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  418. for (i = 0; i < num_hw_events; i++) {
  419. temp = &hw_event_map[i];
  420. if ((temp->start_idx > event_idx && event_idx < temp->end_idx) ||
  421. (temp->start_idx < event_idx && event_idx > temp->end_idx))
  422. continue;
  423. /* For raw events, event data is used as the select value */
  424. if ((event_idx == SBI_PMU_EVENT_RAW_IDX) && temp->select != data)
  425. continue;
  426. /* Fixed counters should not be part of the search */
  427. ctr_mask = temp->counters & (cmask << cbase) &
  428. (~SBI_PMU_FIXED_CTR_MASK);
  429. for_each_set_bit_from(cbase, &ctr_mask, SBI_PMU_HW_CTR_MAX) {
  430. /**
  431. * Some of the platform may not support mcountinhibit.
  432. * Checking the active_events is enough for them
  433. */
  434. if (active_events[hartid][cbase] != SBI_PMU_EVENT_IDX_INVALID)
  435. continue;
  436. /* If mcountinhibit is supported, the bit must be enabled */
  437. if ((sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT)) &&
  438. !__test_bit(cbase, &mctr_inhbt))
  439. continue;
  440. /* We found a valid counter that is not started yet */
  441. ctr_idx = cbase;
  442. }
  443. }
  444. if (ctr_idx == SBI_ENOTSUPP) {
  445. /**
  446. * We can't find any programmable counters for cycle/instret.
  447. * Return the fixed counter as they are mandatory anyways.
  448. */
  449. if (fixed_ctr >= 0)
  450. return fixed_ctr;
  451. else
  452. return SBI_EFAIL;
  453. }
  454. ret = pmu_update_hw_mhpmevent(temp, ctr_idx, flags, event_idx, data);
  455. if (!ret)
  456. ret = ctr_idx;
  457. return ret;
  458. }
  459. /**
  460. * Any firmware counter can map to any firmware event.
  461. * Thus, select the first available fw counter after sanity
  462. * check.
  463. */
  464. static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, u32 hartid)
  465. {
  466. int i = 0;
  467. int fw_base;
  468. unsigned long ctr_mask = cmask << cbase;
  469. if (cbase <= num_hw_ctrs)
  470. fw_base = num_hw_ctrs + 1;
  471. else
  472. fw_base = cbase;
  473. for (i = fw_base; i < total_ctrs; i++)
  474. if ((active_events[hartid][i] == SBI_PMU_EVENT_IDX_INVALID) &&
  475. ((1UL << i) & ctr_mask))
  476. return i;
  477. return SBI_ENOTSUPP;
  478. }
  479. int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
  480. unsigned long flags, unsigned long event_idx,
  481. uint64_t event_data)
  482. {
  483. int ctr_idx = SBI_ENOTSUPP;
  484. u32 hartid = current_hartid();
  485. int event_type = get_cidx_type(event_idx);
  486. struct sbi_pmu_fw_event *fevent;
  487. uint32_t fw_evt_code;
  488. unsigned long tmp = cidx_mask << cidx_base;
  489. /* Do a basic sanity check of counter base & mask */
  490. if (__fls(tmp) >= total_ctrs || event_type >= SBI_PMU_EVENT_TYPE_MAX)
  491. return SBI_EINVAL;
  492. if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) {
  493. /* The caller wants to skip the match because it already knows the
  494. * counter idx for the given event. Verify that the counter idx
  495. * is still valid.
  496. */
  497. if (active_events[hartid][cidx_base] == SBI_PMU_EVENT_IDX_INVALID)
  498. return SBI_EINVAL;
  499. ctr_idx = cidx_base;
  500. goto skip_match;
  501. }
  502. if (event_type == SBI_PMU_EVENT_TYPE_FW) {
  503. /* Any firmware counter can be used track any firmware event */
  504. ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, hartid);
  505. } else {
  506. ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx,
  507. event_data);
  508. }
  509. if (ctr_idx < 0)
  510. return SBI_ENOTSUPP;
  511. active_events[hartid][ctr_idx] = event_idx;
  512. skip_match:
  513. if (event_type == SBI_PMU_EVENT_TYPE_HW) {
  514. if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE)
  515. pmu_ctr_write_hw(ctr_idx, 0);
  516. if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
  517. pmu_ctr_start_hw(ctr_idx, 0, false);
  518. } else if (event_type == SBI_PMU_EVENT_TYPE_FW) {
  519. fw_evt_code = get_cidx_code(event_idx);
  520. fevent = &fw_event_map[hartid][fw_evt_code];
  521. if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE)
  522. fevent->curr_count = 0;
  523. if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
  524. fevent->bStarted = TRUE;
  525. }
  526. return ctr_idx;
  527. }
  528. inline int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id)
  529. {
  530. u32 hartid = current_hartid();
  531. struct sbi_pmu_fw_event *fevent;
  532. if (unlikely(fw_id >= SBI_PMU_FW_MAX))
  533. return SBI_EINVAL;
  534. fevent = &fw_event_map[hartid][fw_id];
  535. /* PMU counters will be only enabled during performance debugging */
  536. if (unlikely(fevent->bStarted))
  537. fevent->curr_count++;
  538. return 0;
  539. }
  540. unsigned long sbi_pmu_num_ctr(void)
  541. {
  542. return (num_hw_ctrs + SBI_PMU_FW_CTR_MAX);
  543. }
  544. int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info)
  545. {
  546. union sbi_pmu_ctr_info cinfo = {0};
  547. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  548. /* Sanity check. Counter1 is not mapped at all */
  549. if (cidx >= total_ctrs || cidx == 1)
  550. return SBI_EINVAL;
  551. /* We have 31 HW counters with 31 being the last index(MHPMCOUNTER31) */
  552. if (cidx <= num_hw_ctrs) {
  553. cinfo.type = SBI_PMU_CTR_TYPE_HW;
  554. cinfo.csr = CSR_CYCLE + cidx;
  555. /* mcycle & minstret are always 64 bit */
  556. if (cidx == 0 || cidx == 2)
  557. cinfo.width = 63;
  558. else
  559. cinfo.width = sbi_hart_mhpm_bits(scratch) - 1;
  560. } else {
  561. /* it's a firmware counter */
  562. cinfo.type = SBI_PMU_CTR_TYPE_FW;
  563. /* Firmware counters are XLEN bits wide */
  564. cinfo.width = BITS_PER_LONG - 1;
  565. }
  566. *ctr_info = cinfo.value;
  567. return 0;
  568. }
  569. static void pmu_reset_event_map(u32 hartid)
  570. {
  571. int j;
  572. /* Initialize the counter to event mapping table */
  573. for (j = 3; j < total_ctrs; j++)
  574. active_events[hartid][j] = SBI_PMU_EVENT_IDX_INVALID;
  575. for (j = 0; j < SBI_PMU_FW_CTR_MAX; j++)
  576. sbi_memset(&fw_event_map[hartid][j], 0,
  577. sizeof(struct sbi_pmu_fw_event));
  578. }
  579. void sbi_pmu_exit(struct sbi_scratch *scratch)
  580. {
  581. u32 hartid = current_hartid();
  582. if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT))
  583. csr_write(CSR_MCOUNTINHIBIT, 0xFFFFFFF8);
  584. csr_write(CSR_MCOUNTEREN, -1);
  585. pmu_reset_event_map(hartid);
  586. }
  587. int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
  588. {
  589. const struct sbi_platform *plat;
  590. u32 hartid = current_hartid();
  591. if (cold_boot) {
  592. plat = sbi_platform_ptr(scratch);
  593. /* Initialize hw pmu events */
  594. sbi_platform_pmu_init(plat);
  595. /* mcycle & minstret is available always */
  596. num_hw_ctrs = sbi_hart_mhpm_count(scratch) + 2;
  597. total_ctrs = num_hw_ctrs + SBI_PMU_FW_CTR_MAX;
  598. }
  599. pmu_reset_event_map(hartid);
  600. /* First three counters are fixed by the priv spec and we enable it by default */
  601. active_events[hartid][0] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET |
  602. SBI_PMU_HW_CPU_CYCLES;
  603. active_events[hartid][1] = SBI_PMU_EVENT_IDX_INVALID;
  604. active_events[hartid][2] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET |
  605. SBI_PMU_HW_INSTRUCTIONS;
  606. return 0;
  607. }