sbi_system.c 4.5 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. * Nick Kossifidis <mick@ics.forth.gr>
  9. */
  10. #include <sbi/riscv_asm.h>
  11. #include <sbi/sbi_bitops.h>
  12. #include <sbi/sbi_domain.h>
  13. #include <sbi/sbi_hart.h>
  14. #include <sbi/sbi_hsm.h>
  15. #include <sbi/sbi_platform.h>
  16. #include <sbi/sbi_system.h>
  17. #include <sbi/sbi_ipi.h>
  18. #include <sbi/sbi_init.h>
  19. static SBI_LIST_HEAD(reset_devices_list);
  20. const struct sbi_system_reset_device *sbi_system_reset_get_device(
  21. u32 reset_type, u32 reset_reason)
  22. {
  23. struct sbi_system_reset_device *reset_dev = NULL;
  24. struct sbi_dlist *pos;
  25. /** lowest priority - any non zero is our candidate */
  26. int priority = 0;
  27. /* Check each reset device registered for supported reset type */
  28. sbi_list_for_each(pos, &(reset_devices_list)) {
  29. struct sbi_system_reset_device *dev =
  30. to_system_reset_device(pos);
  31. if (dev->system_reset_check) {
  32. int status = dev->system_reset_check(reset_type,
  33. reset_reason);
  34. /** reset_type not supported */
  35. if (status == 0)
  36. continue;
  37. if (status > priority) {
  38. reset_dev = dev;
  39. priority = status;
  40. }
  41. }
  42. }
  43. return reset_dev;
  44. }
  45. void sbi_system_reset_add_device(struct sbi_system_reset_device *dev)
  46. {
  47. if (!dev || !dev->system_reset_check)
  48. return;
  49. sbi_list_add(&(dev->node), &(reset_devices_list));
  50. }
  51. bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason)
  52. {
  53. return !!sbi_system_reset_get_device(reset_type, reset_reason);
  54. }
  55. void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
  56. {
  57. ulong hbase = 0, hmask;
  58. u32 cur_hartid = current_hartid();
  59. struct sbi_domain *dom = sbi_domain_thishart_ptr();
  60. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  61. /* Send HALT IPI to every hart other than the current hart */
  62. while (!sbi_hsm_hart_interruptible_mask(dom, hbase, &hmask)) {
  63. if (hbase <= cur_hartid)
  64. hmask &= ~(1UL << (cur_hartid - hbase));
  65. if (hmask)
  66. sbi_ipi_send_halt(hmask, hbase);
  67. hbase += BITS_PER_LONG;
  68. }
  69. /* Stop current HART */
  70. sbi_hsm_hart_stop(scratch, false);
  71. /* Platform specific reset if domain allowed system reset */
  72. if (dom->system_reset_allowed) {
  73. const struct sbi_system_reset_device *dev =
  74. sbi_system_reset_get_device(reset_type, reset_reason);
  75. if (dev)
  76. dev->system_reset(reset_type, reset_reason);
  77. }
  78. /* If platform specific reset did not work then do sbi_exit() */
  79. sbi_exit(scratch);
  80. }
  81. static const struct sbi_system_suspend_device *suspend_dev = NULL;
  82. const struct sbi_system_suspend_device *sbi_system_suspend_get_device(void)
  83. {
  84. return suspend_dev;
  85. }
  86. void sbi_system_suspend_set_device(struct sbi_system_suspend_device *dev)
  87. {
  88. if (!dev || suspend_dev)
  89. return;
  90. suspend_dev = dev;
  91. }
  92. bool sbi_system_suspend_supported(u32 sleep_type)
  93. {
  94. return suspend_dev && suspend_dev->system_suspend_check &&
  95. suspend_dev->system_suspend_check(sleep_type);
  96. }
  97. int sbi_system_suspend(u32 sleep_type, ulong resume_addr, ulong opaque)
  98. {
  99. int ret = SBI_ENOTSUPP;
  100. const struct sbi_domain *dom = sbi_domain_thishart_ptr();
  101. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  102. void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;
  103. unsigned int hartid = current_hartid();
  104. unsigned long prev_mode;
  105. unsigned long i;
  106. if (!dom || !dom->system_suspend_allowed)
  107. return SBI_EFAIL;
  108. if (!suspend_dev || !suspend_dev->system_suspend)
  109. return SBI_EFAIL;
  110. if (!sbi_system_suspend_supported(sleep_type))
  111. return SBI_ENOTSUPP;
  112. prev_mode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
  113. if (prev_mode != PRV_S && prev_mode != PRV_U)
  114. return SBI_EFAIL;
  115. sbi_hartmask_for_each_hart(i, &dom->assigned_harts) {
  116. if (i == hartid)
  117. continue;
  118. if (__sbi_hsm_hart_get_state(i) != SBI_HSM_STATE_STOPPED)
  119. return SBI_EFAIL;
  120. }
  121. if (!sbi_domain_check_addr(dom, resume_addr, prev_mode,
  122. SBI_DOMAIN_EXECUTE))
  123. return SBI_EINVALID_ADDR;
  124. if (!sbi_hsm_hart_change_state(scratch, SBI_HSM_STATE_STARTED,
  125. SBI_HSM_STATE_SUSPENDED))
  126. return SBI_EFAIL;
  127. /* Prepare for resume */
  128. scratch->next_mode = prev_mode;
  129. scratch->next_addr = resume_addr;
  130. scratch->next_arg1 = opaque;
  131. __sbi_hsm_suspend_non_ret_save(scratch);
  132. /* Suspend */
  133. ret = suspend_dev->system_suspend(sleep_type, scratch->warmboot_addr);
  134. if (ret != SBI_OK) {
  135. if (!sbi_hsm_hart_change_state(scratch, SBI_HSM_STATE_SUSPENDED,
  136. SBI_HSM_STATE_STARTED))
  137. sbi_hart_hang();
  138. return ret;
  139. }
  140. /* Resume */
  141. jump_warmboot();
  142. __builtin_unreachable();
  143. }