dubhe_cache.S 1.2 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2022 StarFive Technology Co., Ltd.
  5. *
  6. * Author: Chee Hong Ang <cheehong.ang@linux.starfivetech.com>
  7. *
  8. */
  9. #define DUBHE_L2_CACHELINE_SIZE 0x40
  10. /*
  11. * __sbi_dubhe_L2_inv_range(start,len)
  12. *
  13. * Invalidate the L2 cache within the specified region
  14. *
  15. * start - physical start address of region
  16. * len - size of memory region
  17. */
  18. .align 3
  19. .global __sbi_dubhe_L2_inv_range
  20. __sbi_dubhe_L2_inv_range:
  21. beqz a1, 2f
  22. li t0, DUBHE_L2_CACHELINE_SIZE
  23. addi t1, t0, -1
  24. add a1, a1, a0 /* Compute end address */
  25. not t2, t1
  26. and a0, a0, t2
  27. 1:
  28. /* CDISCARD.L2 rs1 = a0 */
  29. fence rw, rw
  30. .insn i 0x73, 0, x0, a0, -0x3A
  31. fence rw, rw
  32. add a0, a0, t0
  33. blt a0, a1, 1b
  34. 2:
  35. ret
  36. /*
  37. * __sbi_dubhe_L2_flush_range(start,len)
  38. *
  39. * Flush and invalidate the L2 cache within the specified region
  40. *
  41. * start - physical start address of region
  42. * len - size of memory region
  43. */
  44. .align 3
  45. .global __sbi_dubhe_L2_flush_range
  46. __sbi_dubhe_L2_flush_range:
  47. beqz a1, 2f
  48. li t0, DUBHE_L2_CACHELINE_SIZE
  49. addi t1, t0, -1
  50. add a1, a1, a0 /* Compute end address */
  51. not t2, t1
  52. and a0, a0, t2
  53. 1:
  54. /* CFLUSH.L2 rs1 = a0 */
  55. fence rw, rw
  56. .insn i 0x73, 0, x0, a0, -0x3C
  57. fence rw, rw
  58. add a0, a0, t0
  59. blt a0, a1, 1b
  60. 2:
  61. ret