platform.c 5.8 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) Nuclei Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * lujun <lujun@nucleisys.com>
  8. * hqfang <578567190@qq.com>
  9. */
  10. #include <sbi/riscv_asm.h>
  11. #include <sbi/riscv_io.h>
  12. #include <sbi/riscv_encoding.h>
  13. #include <sbi/sbi_console.h>
  14. #include <sbi/sbi_const.h>
  15. #include <sbi/sbi_platform.h>
  16. #include <sbi/sbi_system.h>
  17. #include <sbi_utils/fdt/fdt_helper.h>
  18. #include <sbi_utils/fdt/fdt_fixup.h>
  19. #include <sbi_utils/ipi/aclint_mswi.h>
  20. #include <sbi_utils/irqchip/plic.h>
  21. #include <sbi_utils/serial/sifive-uart.h>
  22. #include <sbi_utils/timer/aclint_mtimer.h>
  23. /* clang-format off */
  24. #define UX600_HART_COUNT 1
  25. #define UX600_TIMER_FREQ 32768
  26. /* Nuclei timer base address */
  27. #define UX600_NUCLEI_TIMER_ADDR 0x2000000
  28. #define UX600_NUCLEI_TIMER_MSFTRST_OFS 0xFF0
  29. #define UX600_NUCLEI_TIMER_MSFTRST_KEY 0x80000A5F
  30. /* The clint compatiable timer offset is 0x1000 against nuclei timer */
  31. #define UX600_CLINT_TIMER_ADDR (UX600_NUCLEI_TIMER_ADDR + 0x1000)
  32. #define UX600_ACLINT_MSWI_ADDR (UX600_CLINT_TIMER_ADDR + \
  33. CLINT_MSWI_OFFSET)
  34. #define UX600_ACLINT_MTIMER_ADDR (UX600_CLINT_TIMER_ADDR + \
  35. CLINT_MTIMER_OFFSET)
  36. #define UX600_PLIC_ADDR 0x8000000
  37. #define UX600_PLIC_NUM_SOURCES 0x35
  38. #define UX600_PLIC_NUM_PRIORITIES 7
  39. #define UX600_UART0_ADDR 0x10013000
  40. #define UX600_UART1_ADDR 0x10023000
  41. #define UX600_DEBUG_UART UX600_UART0_ADDR
  42. #ifndef UX600_UART_BAUDRATE
  43. #define UX600_UART_BAUDRATE 57600
  44. #endif
  45. #define UX600_GPIO_ADDR 0x10012000
  46. #define UX600_GPIO_IOF_EN_OFS 0x38
  47. #define UX600_GPIO_IOF_SEL_OFS 0x3C
  48. #define UX600_GPIO_IOF_UART0_MASK 0x00030000
  49. #define UX600_TIMER_VALUE() readl((void *)UX600_NUCLEI_TIMER_ADDR)
  50. /* clang-format on */
  51. static u32 ux600_clk_freq = 8000000;
  52. static struct plic_data plic = {
  53. .addr = UX600_PLIC_ADDR,
  54. .num_src = UX600_PLIC_NUM_SOURCES,
  55. };
  56. static struct aclint_mswi_data mswi = {
  57. .addr = UX600_ACLINT_MSWI_ADDR,
  58. .size = ACLINT_MSWI_SIZE,
  59. .first_hartid = 0,
  60. .hart_count = UX600_HART_COUNT,
  61. };
  62. static struct aclint_mtimer_data mtimer = {
  63. .mtime_freq = UX600_TIMER_FREQ,
  64. .mtime_addr = UX600_ACLINT_MTIMER_ADDR +
  65. ACLINT_DEFAULT_MTIME_OFFSET,
  66. .mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
  67. .mtimecmp_addr = UX600_ACLINT_MTIMER_ADDR +
  68. ACLINT_DEFAULT_MTIMECMP_OFFSET,
  69. .mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
  70. .first_hartid = 0,
  71. .hart_count = UX600_HART_COUNT,
  72. .has_64bit_mmio = TRUE,
  73. };
  74. static u32 measure_cpu_freq(u32 n)
  75. {
  76. u32 start_mtime, delta_mtime;
  77. u32 mtime_freq = UX600_TIMER_FREQ;
  78. u32 tmp = (u32)UX600_TIMER_VALUE();
  79. u32 start_mcycle, delta_mcycle, freq;
  80. /* Don't start measuring until we see an mtime tick */
  81. do {
  82. start_mtime = (u32)UX600_TIMER_VALUE();
  83. } while (start_mtime == tmp);
  84. start_mcycle = csr_read(mcycle);
  85. do {
  86. delta_mtime = (u32)UX600_TIMER_VALUE() - start_mtime;
  87. } while (delta_mtime < n);
  88. delta_mcycle = csr_read(mcycle) - start_mcycle;
  89. freq = (delta_mcycle / delta_mtime) * mtime_freq
  90. + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
  91. return freq;
  92. }
  93. static u32 ux600_get_clk_freq(void)
  94. {
  95. u32 cpu_freq;
  96. /* warm up */
  97. measure_cpu_freq(1);
  98. /* measure for real */
  99. cpu_freq = measure_cpu_freq(100);
  100. return cpu_freq;
  101. }
  102. static int ux600_system_reset_check(u32 type, u32 reason)
  103. {
  104. return 1;
  105. }
  106. static void ux600_system_reset(u32 type, u32 reason)
  107. {
  108. /* Reset system using MSFTRST register in Nuclei Timer. */
  109. writel(UX600_NUCLEI_TIMER_MSFTRST_KEY, (void *)(UX600_NUCLEI_TIMER_ADDR
  110. + UX600_NUCLEI_TIMER_MSFTRST_OFS));
  111. while(1);
  112. }
  113. static struct sbi_system_reset_device ux600_reset = {
  114. .name = "nuclei_ux600_reset",
  115. .system_reset_check = ux600_system_reset_check,
  116. .system_reset = ux600_system_reset
  117. };
  118. static int ux600_early_init(bool cold_boot)
  119. {
  120. u32 regval;
  121. if (cold_boot)
  122. sbi_system_reset_add_device(&ux600_reset);
  123. /* Measure CPU Frequency using Timer */
  124. ux600_clk_freq = ux600_get_clk_freq();
  125. /* Init GPIO UART pinmux */
  126. regval = readl((void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_SEL_OFS)) &
  127. ~UX600_GPIO_IOF_UART0_MASK;
  128. writel(regval, (void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_SEL_OFS));
  129. regval = readl((void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_EN_OFS)) |
  130. UX600_GPIO_IOF_UART0_MASK;
  131. writel(regval, (void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_EN_OFS));
  132. return 0;
  133. }
  134. static void ux600_modify_dt(void *fdt)
  135. {
  136. fdt_fixups(fdt);
  137. }
  138. static int ux600_final_init(bool cold_boot)
  139. {
  140. void *fdt;
  141. if (!cold_boot)
  142. return 0;
  143. fdt = fdt_get_address();
  144. ux600_modify_dt(fdt);
  145. return 0;
  146. }
  147. static int ux600_console_init(void)
  148. {
  149. return sifive_uart_init(UX600_DEBUG_UART, ux600_clk_freq,
  150. UX600_UART_BAUDRATE);
  151. }
  152. static int ux600_irqchip_init(bool cold_boot)
  153. {
  154. int rc;
  155. u32 hartid = current_hartid();
  156. if (cold_boot) {
  157. rc = plic_cold_irqchip_init(&plic);
  158. if (rc)
  159. return rc;
  160. }
  161. return plic_warm_irqchip_init(&plic, (hartid) ? (2 * hartid - 1) : 0,
  162. (hartid) ? (2 * hartid) : -1);
  163. }
  164. static int ux600_ipi_init(bool cold_boot)
  165. {
  166. int rc;
  167. if (cold_boot) {
  168. rc = aclint_mswi_cold_init(&mswi);
  169. if (rc)
  170. return rc;
  171. }
  172. return aclint_mswi_warm_init();
  173. }
  174. static int ux600_timer_init(bool cold_boot)
  175. {
  176. int rc;
  177. if (cold_boot) {
  178. rc = aclint_mtimer_cold_init(&mtimer, NULL);
  179. if (rc)
  180. return rc;
  181. }
  182. return aclint_mtimer_warm_init();
  183. }
  184. const struct sbi_platform_operations platform_ops = {
  185. .early_init = ux600_early_init,
  186. .final_init = ux600_final_init,
  187. .console_init = ux600_console_init,
  188. .irqchip_init = ux600_irqchip_init,
  189. .ipi_init = ux600_ipi_init,
  190. .timer_init = ux600_timer_init,
  191. };
  192. const struct sbi_platform platform = {
  193. .opensbi_version = OPENSBI_VERSION,
  194. .platform_version = SBI_PLATFORM_VERSION(0x0U, 0x01U),
  195. .name = "Nuclei UX600",
  196. .features = SBI_PLATFORM_DEFAULT_FEATURES,
  197. .hart_count = UX600_HART_COUNT,
  198. .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
  199. .platform_ops_addr = (unsigned long)&platform_ops
  200. };