plic.c 2.7 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_io.h>
  10. #include <sbi/riscv_encoding.h>
  11. #include <sbi/sbi_console.h>
  12. #include <sbi/sbi_string.h>
  13. #include <sbi_utils/irqchip/plic.h>
  14. #include <libfdt.h>
  15. #include <fdt.h>
  16. #define PLIC_PRIORITY_BASE 0x0
  17. #define PLIC_PENDING_BASE 0x1000
  18. #define PLIC_ENABLE_BASE 0x2000
  19. #define PLIC_ENABLE_STRIDE 0x80
  20. #define PLIC_CONTEXT_BASE 0x200000
  21. #define PLIC_CONTEXT_STRIDE 0x1000
  22. static u32 plic_hart_count;
  23. static u32 plic_num_sources;
  24. static volatile void *plic_base;
  25. static void plic_set_priority(u32 source, u32 val)
  26. {
  27. volatile void *plic_priority =
  28. plic_base + PLIC_PRIORITY_BASE + 4 * source;
  29. writel(val, plic_priority);
  30. }
  31. static void plic_set_thresh(u32 cntxid, u32 val)
  32. {
  33. volatile void *plic_thresh =
  34. plic_base + PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
  35. writel(val, plic_thresh);
  36. }
  37. static void plic_set_ie(u32 cntxid, u32 word_index, u32 val)
  38. {
  39. volatile void *plic_ie =
  40. plic_base + PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid;
  41. writel(val, plic_ie + word_index * 4);
  42. }
  43. void plic_fdt_fixup(void *fdt, const char *compat)
  44. {
  45. u32 *cells;
  46. int i, cells_count;
  47. u32 plic_off;
  48. plic_off = fdt_node_offset_by_compatible(fdt, 0, compat);
  49. if (plic_off < 0)
  50. return;
  51. cells = (u32 *)fdt_getprop(fdt, plic_off,
  52. "interrupts-extended", &cells_count);
  53. if (!cells)
  54. return;
  55. cells_count = cells_count / sizeof(u32);
  56. if (!cells_count)
  57. return;
  58. for (i = 0; i < (cells_count / 2); i++) {
  59. if (fdt32_to_cpu(cells[2 * i + 1]) == IRQ_M_EXT)
  60. cells[2 * i + 1] = fdt32_to_cpu(0xffffffff);
  61. }
  62. }
  63. int plic_warm_irqchip_init(u32 target_hart, int m_cntx_id, int s_cntx_id)
  64. {
  65. size_t i, ie_words = plic_num_sources / 32 + 1;
  66. if (plic_hart_count <= target_hart)
  67. return -1;
  68. /* By default, disable all IRQs for M-mode of target HART */
  69. if (m_cntx_id > -1) {
  70. for (i = 0; i < ie_words; i++)
  71. plic_set_ie(m_cntx_id, i, 0);
  72. }
  73. /* By default, disable all IRQs for S-mode of target HART */
  74. if (s_cntx_id > -1) {
  75. for (i = 0; i < ie_words; i++)
  76. plic_set_ie(s_cntx_id, i, 0);
  77. }
  78. /* By default, enable M-mode threshold */
  79. if (m_cntx_id > -1)
  80. plic_set_thresh(m_cntx_id, 1);
  81. /* By default, disable S-mode threshold */
  82. if (s_cntx_id > -1)
  83. plic_set_thresh(s_cntx_id, 0);
  84. return 0;
  85. }
  86. int plic_cold_irqchip_init(unsigned long base, u32 num_sources, u32 hart_count)
  87. {
  88. int i;
  89. plic_hart_count = hart_count;
  90. plic_num_sources = num_sources;
  91. plic_base = (void *)base;
  92. /* Configure default priorities of all IRQs */
  93. for (i = 1; i <= plic_num_sources; i++)
  94. plic_set_priority(i, 1);
  95. return 0;
  96. }