sbi_system.c 5.2 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. * Nick Kossifidis <mick@ics.forth.gr>
  9. */
  10. #include <sbi/riscv_asm.h>
  11. #include <sbi/sbi_bitops.h>
  12. #include <sbi/sbi_domain.h>
  13. #include <sbi/sbi_hart.h>
  14. #include <sbi/sbi_hsm.h>
  15. #include <sbi/sbi_platform.h>
  16. #include <sbi/sbi_system.h>
  17. #include <sbi/sbi_ipi.h>
  18. #include <sbi/sbi_init.h>
  19. #include <sbi/sbi_timer.h>
  20. static SBI_LIST_HEAD(reset_devices_list);
  21. const struct sbi_system_reset_device *sbi_system_reset_get_device(
  22. u32 reset_type, u32 reset_reason)
  23. {
  24. struct sbi_system_reset_device *reset_dev = NULL;
  25. struct sbi_dlist *pos;
  26. /** lowest priority - any non zero is our candidate */
  27. int priority = 0;
  28. /* Check each reset device registered for supported reset type */
  29. sbi_list_for_each(pos, &(reset_devices_list)) {
  30. struct sbi_system_reset_device *dev =
  31. to_system_reset_device(pos);
  32. if (dev->system_reset_check) {
  33. int status = dev->system_reset_check(reset_type,
  34. reset_reason);
  35. /** reset_type not supported */
  36. if (status == 0)
  37. continue;
  38. if (status > priority) {
  39. reset_dev = dev;
  40. priority = status;
  41. }
  42. }
  43. }
  44. return reset_dev;
  45. }
  46. void sbi_system_reset_add_device(struct sbi_system_reset_device *dev)
  47. {
  48. if (!dev || !dev->system_reset_check)
  49. return;
  50. sbi_list_add(&(dev->node), &(reset_devices_list));
  51. }
  52. bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason)
  53. {
  54. return !!sbi_system_reset_get_device(reset_type, reset_reason);
  55. }
  56. void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
  57. {
  58. ulong hbase = 0, hmask;
  59. u32 cur_hartid = current_hartid();
  60. struct sbi_domain *dom = sbi_domain_thishart_ptr();
  61. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  62. /* Send HALT IPI to every hart other than the current hart */
  63. while (!sbi_hsm_hart_interruptible_mask(dom, hbase, &hmask)) {
  64. if (hbase <= cur_hartid)
  65. hmask &= ~(1UL << (cur_hartid - hbase));
  66. if (hmask)
  67. sbi_ipi_send_halt(hmask, hbase);
  68. hbase += BITS_PER_LONG;
  69. }
  70. /* Stop current HART */
  71. sbi_hsm_hart_stop(scratch, false);
  72. /* Platform specific reset if domain allowed system reset */
  73. if (dom->system_reset_allowed) {
  74. const struct sbi_system_reset_device *dev =
  75. sbi_system_reset_get_device(reset_type, reset_reason);
  76. if (dev)
  77. dev->system_reset(reset_type, reset_reason);
  78. }
  79. /* If platform specific reset did not work then do sbi_exit() */
  80. sbi_exit(scratch);
  81. }
  82. static const struct sbi_system_suspend_device *suspend_dev = NULL;
  83. const struct sbi_system_suspend_device *sbi_system_suspend_get_device(void)
  84. {
  85. return suspend_dev;
  86. }
  87. void sbi_system_suspend_set_device(struct sbi_system_suspend_device *dev)
  88. {
  89. if (!dev || suspend_dev)
  90. return;
  91. suspend_dev = dev;
  92. }
  93. static int sbi_system_suspend_test_check(u32 sleep_type)
  94. {
  95. return sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND;
  96. }
  97. static int sbi_system_suspend_test_suspend(u32 sleep_type,
  98. unsigned long mmode_resume_addr)
  99. {
  100. if (sleep_type != SBI_SUSP_SLEEP_TYPE_SUSPEND)
  101. return SBI_EINVAL;
  102. sbi_timer_mdelay(5000);
  103. /* Wait for interrupt */
  104. wfi();
  105. return SBI_OK;
  106. }
  107. static struct sbi_system_suspend_device sbi_system_suspend_test = {
  108. .name = "system-suspend-test",
  109. .system_suspend_check = sbi_system_suspend_test_check,
  110. .system_suspend = sbi_system_suspend_test_suspend,
  111. };
  112. void sbi_system_suspend_test_enable(void)
  113. {
  114. sbi_system_suspend_set_device(&sbi_system_suspend_test);
  115. }
  116. bool sbi_system_suspend_supported(u32 sleep_type)
  117. {
  118. return suspend_dev && suspend_dev->system_suspend_check &&
  119. suspend_dev->system_suspend_check(sleep_type);
  120. }
  121. int sbi_system_suspend(u32 sleep_type, ulong resume_addr, ulong opaque)
  122. {
  123. int ret = SBI_ENOTSUPP;
  124. const struct sbi_domain *dom = sbi_domain_thishart_ptr();
  125. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  126. void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;
  127. unsigned int hartid = current_hartid();
  128. unsigned long prev_mode;
  129. unsigned long i;
  130. if (!dom || !dom->system_suspend_allowed)
  131. return SBI_EFAIL;
  132. if (!suspend_dev || !suspend_dev->system_suspend)
  133. return SBI_EFAIL;
  134. if (!sbi_system_suspend_supported(sleep_type))
  135. return SBI_ENOTSUPP;
  136. prev_mode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
  137. if (prev_mode != PRV_S && prev_mode != PRV_U)
  138. return SBI_EFAIL;
  139. sbi_hartmask_for_each_hart(i, &dom->assigned_harts) {
  140. if (i == hartid)
  141. continue;
  142. if (__sbi_hsm_hart_get_state(i) != SBI_HSM_STATE_STOPPED)
  143. return SBI_EFAIL;
  144. }
  145. if (!sbi_domain_check_addr(dom, resume_addr, prev_mode,
  146. SBI_DOMAIN_EXECUTE))
  147. return SBI_EINVALID_ADDR;
  148. if (!sbi_hsm_hart_change_state(scratch, SBI_HSM_STATE_STARTED,
  149. SBI_HSM_STATE_SUSPENDED))
  150. return SBI_EFAIL;
  151. /* Prepare for resume */
  152. scratch->next_mode = prev_mode;
  153. scratch->next_addr = resume_addr;
  154. scratch->next_arg1 = opaque;
  155. __sbi_hsm_suspend_non_ret_save(scratch);
  156. /* Suspend */
  157. ret = suspend_dev->system_suspend(sleep_type, scratch->warmboot_addr);
  158. if (ret != SBI_OK) {
  159. if (!sbi_hsm_hart_change_state(scratch, SBI_HSM_STATE_SUSPENDED,
  160. SBI_HSM_STATE_STARTED))
  161. sbi_hart_hang();
  162. return ret;
  163. }
  164. /* Resume */
  165. jump_warmboot();
  166. __builtin_unreachable();
  167. }