sbi_pmu.c 25 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/sbi_bitops.h>
  11. #include <sbi/sbi_console.h>
  12. #include <sbi/sbi_ecall_interface.h>
  13. #include <sbi/sbi_hart.h>
  14. #include <sbi/sbi_hartmask.h>
  15. #include <sbi/sbi_platform.h>
  16. #include <sbi/sbi_pmu.h>
  17. #include <sbi/sbi_scratch.h>
  18. #include <sbi/sbi_string.h>
  19. /** Information about hardware counters */
  20. struct sbi_pmu_hw_event {
  21. uint32_t counters;
  22. uint32_t start_idx;
  23. uint32_t end_idx;
  24. /* Event selector value used only for raw events. The event select value
  25. * can be a even id or a selector value for set of events encoded in few
  26. * bits. In case latter, the bits used for encoding of the events should
  27. * be zeroed out in the select value.
  28. */
  29. uint64_t select;
  30. /**
  31. * The select_mask indicates which bits are encoded for the event(s).
  32. */
  33. uint64_t select_mask;
  34. };
  35. /* Information about PMU counters as per SBI specification */
  36. union sbi_pmu_ctr_info {
  37. unsigned long value;
  38. struct {
  39. unsigned long csr:12;
  40. unsigned long width:6;
  41. #if __riscv_xlen == 32
  42. unsigned long reserved:13;
  43. #else
  44. unsigned long reserved:45;
  45. #endif
  46. unsigned long type:1;
  47. };
  48. };
  49. /* Platform specific PMU device */
  50. static const struct sbi_pmu_device *pmu_dev = NULL;
  51. /* Mapping between event range and possible counters */
  52. static struct sbi_pmu_hw_event hw_event_map[SBI_PMU_HW_EVENT_MAX] = {0};
  53. /* counter to enabled event mapping */
  54. static uint32_t active_events[SBI_HARTMASK_MAX_BITS][SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX];
  55. /* Bitmap of firmware counters started on each HART */
  56. #if SBI_PMU_FW_CTR_MAX >= BITS_PER_LONG
  57. #error "Can't handle firmware counters beyond BITS_PER_LONG"
  58. #endif
  59. static unsigned long fw_counters_started[SBI_HARTMASK_MAX_BITS];
  60. /*
  61. * Counter values for SBI firmware events and event codes for platform
  62. * firmware events. Both are mutually exclusive and hence can optimally share
  63. * the same memory.
  64. */
  65. static uint64_t fw_counters_data[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_CTR_MAX] = {0};
  66. /* Maximum number of hardware events available */
  67. static uint32_t num_hw_events;
  68. /* Maximum number of hardware counters available */
  69. static uint32_t num_hw_ctrs;
  70. /* Maximum number of counters available */
  71. static uint32_t total_ctrs;
  72. /* Helper macros to retrieve event idx and code type */
  73. #define get_cidx_type(x) ((x & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16)
  74. #define get_cidx_code(x) (x & SBI_PMU_EVENT_IDX_CODE_MASK)
  75. /**
  76. * Perform a sanity check on event & counter mappings with event range overlap check
  77. * @param evtA Pointer to the existing hw event structure
  78. * @param evtB Pointer to the new hw event structure
  79. *
  80. * Return false if the range doesn't overlap, true otherwise
  81. */
  82. static bool pmu_event_range_overlap(struct sbi_pmu_hw_event *evtA,
  83. struct sbi_pmu_hw_event *evtB)
  84. {
  85. /* check if the range of events overlap with a previous entry */
  86. if (((evtA->end_idx < evtB->start_idx) && (evtA->end_idx < evtB->end_idx)) ||
  87. ((evtA->start_idx > evtB->start_idx) && (evtA->start_idx > evtB->end_idx)))
  88. return false;
  89. return true;
  90. }
  91. static bool pmu_event_select_overlap(struct sbi_pmu_hw_event *evt,
  92. uint64_t select_val, uint64_t select_mask)
  93. {
  94. if ((evt->select == select_val) && (evt->select_mask == select_mask))
  95. return true;
  96. return false;
  97. }
  98. static int pmu_event_validate(unsigned long event_idx, uint64_t edata)
  99. {
  100. uint32_t event_idx_type = get_cidx_type(event_idx);
  101. uint32_t event_idx_code = get_cidx_code(event_idx);
  102. uint32_t event_idx_code_max = -1;
  103. uint32_t cache_ops_result, cache_ops_id, cache_id;
  104. switch(event_idx_type) {
  105. case SBI_PMU_EVENT_TYPE_HW:
  106. event_idx_code_max = SBI_PMU_HW_GENERAL_MAX;
  107. break;
  108. case SBI_PMU_EVENT_TYPE_FW:
  109. if ((event_idx_code >= SBI_PMU_FW_MAX &&
  110. event_idx_code <= SBI_PMU_FW_RESERVED_MAX) ||
  111. event_idx_code > SBI_PMU_FW_PLATFORM)
  112. return SBI_EINVAL;
  113. if (SBI_PMU_FW_PLATFORM == event_idx_code &&
  114. pmu_dev && pmu_dev->fw_event_validate_encoding)
  115. return pmu_dev->fw_event_validate_encoding(edata);
  116. else
  117. event_idx_code_max = SBI_PMU_FW_MAX;
  118. break;
  119. case SBI_PMU_EVENT_TYPE_HW_CACHE:
  120. cache_ops_result = event_idx_code &
  121. SBI_PMU_EVENT_HW_CACHE_OPS_RESULT;
  122. cache_ops_id = (event_idx_code &
  123. SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK) >>
  124. SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET;
  125. cache_id = (event_idx_code &
  126. SBI_PMU_EVENT_HW_CACHE_ID_MASK) >>
  127. SBI_PMU_EVENT_HW_CACHE_ID_OFFSET;
  128. if ((cache_ops_result < SBI_PMU_HW_CACHE_RESULT_MAX) &&
  129. (cache_ops_id < SBI_PMU_HW_CACHE_OP_MAX) &&
  130. (cache_id < SBI_PMU_HW_CACHE_MAX))
  131. return event_idx_type;
  132. else
  133. return SBI_EINVAL;
  134. break;
  135. case SBI_PMU_EVENT_TYPE_HW_RAW:
  136. event_idx_code_max = 1; // event_idx.code should be zero
  137. break;
  138. default:
  139. return SBI_EINVAL;
  140. }
  141. if (event_idx_code < event_idx_code_max)
  142. return event_idx_type;
  143. return SBI_EINVAL;
  144. }
  145. static int pmu_ctr_validate(uint32_t cidx, uint32_t *event_idx_code)
  146. {
  147. uint32_t event_idx_val;
  148. uint32_t event_idx_type;
  149. u32 hartid = current_hartid();
  150. if (cidx >= total_ctrs)
  151. return SBI_EINVAL;
  152. event_idx_val = active_events[hartid][cidx];
  153. event_idx_type = get_cidx_type(event_idx_val);
  154. if (event_idx_val == SBI_PMU_EVENT_IDX_INVALID ||
  155. event_idx_type >= SBI_PMU_EVENT_TYPE_MAX)
  156. return SBI_EINVAL;
  157. *event_idx_code = get_cidx_code(event_idx_val);
  158. return event_idx_type;
  159. }
  160. int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval)
  161. {
  162. int event_idx_type;
  163. uint32_t event_code;
  164. u32 hartid = current_hartid();
  165. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  166. if (event_idx_type != SBI_PMU_EVENT_TYPE_FW)
  167. return SBI_EINVAL;
  168. if ((event_code >= SBI_PMU_FW_MAX &&
  169. event_code <= SBI_PMU_FW_RESERVED_MAX) ||
  170. event_code > SBI_PMU_FW_PLATFORM)
  171. return SBI_EINVAL;
  172. if (SBI_PMU_FW_PLATFORM == event_code) {
  173. if (pmu_dev && pmu_dev->fw_counter_read_value)
  174. *cval = pmu_dev->fw_counter_read_value(cidx -
  175. num_hw_ctrs);
  176. else
  177. *cval = 0;
  178. } else
  179. *cval = fw_counters_data[hartid][cidx - num_hw_ctrs];
  180. return 0;
  181. }
  182. static int pmu_add_hw_event_map(u32 eidx_start, u32 eidx_end, u32 cmap,
  183. uint64_t select, uint64_t select_mask)
  184. {
  185. int i = 0;
  186. bool is_overlap;
  187. struct sbi_pmu_hw_event *event = &hw_event_map[num_hw_events];
  188. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  189. int hw_ctr_avail = sbi_hart_mhpm_count(scratch);
  190. uint32_t ctr_avail_mask = ((uint32_t)(~0) >> (32 - (hw_ctr_avail + 3)));
  191. /* The first two counters are reserved by priv spec */
  192. if (eidx_start > SBI_PMU_HW_INSTRUCTIONS && (cmap & SBI_PMU_FIXED_CTR_MASK))
  193. return SBI_EDENIED;
  194. if (num_hw_events >= SBI_PMU_HW_EVENT_MAX - 1) {
  195. sbi_printf("Can not handle more than %d perf events\n",
  196. SBI_PMU_HW_EVENT_MAX);
  197. return SBI_EFAIL;
  198. }
  199. event->start_idx = eidx_start;
  200. event->end_idx = eidx_end;
  201. /* Sanity check */
  202. for (i = 0; i < num_hw_events; i++) {
  203. if (eidx_start == SBI_PMU_EVENT_RAW_IDX)
  204. /* All raw events have same event idx. Just do sanity check on select */
  205. is_overlap = pmu_event_select_overlap(&hw_event_map[i],
  206. select, select_mask);
  207. else
  208. is_overlap = pmu_event_range_overlap(&hw_event_map[i], event);
  209. if (is_overlap)
  210. goto reset_event;
  211. }
  212. event->select_mask = select_mask;
  213. /* Map the only the counters that are available in the hardware */
  214. event->counters = cmap & ctr_avail_mask;
  215. event->select = select;
  216. num_hw_events++;
  217. return 0;
  218. reset_event:
  219. event->start_idx = 0;
  220. event->end_idx = 0;
  221. return SBI_EINVAL;
  222. }
  223. /**
  224. * Logical counter ids are assigned to hardware counters are assigned consecutively.
  225. * E.g. counter0 must count MCYCLE where counter2 must count minstret. Similarly,
  226. * counterX will mhpmcounterX.
  227. */
  228. int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap)
  229. {
  230. if ((eidx_start > eidx_end) || eidx_start == SBI_PMU_EVENT_RAW_IDX ||
  231. eidx_end == SBI_PMU_EVENT_RAW_IDX)
  232. return SBI_EINVAL;
  233. return pmu_add_hw_event_map(eidx_start, eidx_end, cmap, 0, 0);
  234. }
  235. int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap)
  236. {
  237. return pmu_add_hw_event_map(SBI_PMU_EVENT_RAW_IDX,
  238. SBI_PMU_EVENT_RAW_IDX, cmap, select, select_mask);
  239. }
  240. static int pmu_ctr_enable_irq_hw(int ctr_idx)
  241. {
  242. unsigned long mhpmevent_csr;
  243. unsigned long mhpmevent_curr;
  244. unsigned long mip_val;
  245. unsigned long of_mask;
  246. if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  247. return SBI_EFAIL;
  248. #if __riscv_xlen == 32
  249. mhpmevent_csr = CSR_MHPMEVENT3H + ctr_idx - 3;
  250. of_mask = (uint32_t)~MHPMEVENTH_OF;
  251. #else
  252. mhpmevent_csr = CSR_MHPMEVENT3 + ctr_idx - 3;
  253. of_mask = ~MHPMEVENT_OF;
  254. #endif
  255. mhpmevent_curr = csr_read_num(mhpmevent_csr);
  256. mip_val = csr_read(CSR_MIP);
  257. /**
  258. * Clear out the OF bit so that next interrupt can be enabled.
  259. * This should be done only when the corresponding overflow interrupt
  260. * bit is cleared. That indicates that software has already handled the
  261. * previous interrupts or the hardware yet to set an overflow interrupt.
  262. * Otherwise, there will be race conditions where we may clear the bit
  263. * the software is yet to handle the interrupt.
  264. */
  265. if (!(mip_val & MIP_LCOFIP)) {
  266. mhpmevent_curr &= of_mask;
  267. csr_write_num(mhpmevent_csr, mhpmevent_curr);
  268. }
  269. return 0;
  270. }
  271. static void pmu_ctr_write_hw(uint32_t cidx, uint64_t ival)
  272. {
  273. #if __riscv_xlen == 32
  274. csr_write_num(CSR_MCYCLE + cidx, 0);
  275. csr_write_num(CSR_MCYCLE + cidx, ival & 0xFFFFFFFF);
  276. csr_write_num(CSR_MCYCLEH + cidx, ival >> BITS_PER_LONG);
  277. #else
  278. csr_write_num(CSR_MCYCLE + cidx, ival);
  279. #endif
  280. }
  281. static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
  282. {
  283. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  284. unsigned long mctr_inhbt;
  285. /* Make sure the counter index lies within the range and is not TM bit */
  286. if (cidx >= num_hw_ctrs || cidx == 1)
  287. return SBI_EINVAL;
  288. if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
  289. goto skip_inhibit_update;
  290. /*
  291. * Some of the hardware may not support mcountinhibit but perf stat
  292. * still can work if supervisor mode programs the initial value.
  293. */
  294. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  295. if (!__test_bit(cidx, &mctr_inhbt))
  296. return SBI_EALREADY_STARTED;
  297. __clear_bit(cidx, &mctr_inhbt);
  298. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  299. pmu_ctr_enable_irq_hw(cidx);
  300. if (pmu_dev && pmu_dev->hw_counter_enable_irq)
  301. pmu_dev->hw_counter_enable_irq(cidx);
  302. csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt);
  303. skip_inhibit_update:
  304. if (ival_update)
  305. pmu_ctr_write_hw(cidx, ival);
  306. return 0;
  307. }
  308. int sbi_pmu_irq_bit(void)
  309. {
  310. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  311. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  312. return MIP_LCOFIP;
  313. if (pmu_dev && pmu_dev->hw_counter_irq_bit)
  314. return pmu_dev->hw_counter_irq_bit();
  315. return 0;
  316. }
  317. static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code,
  318. uint64_t event_data, uint64_t ival,
  319. bool ival_update)
  320. {
  321. u32 hartid = current_hartid();
  322. if ((event_code >= SBI_PMU_FW_MAX &&
  323. event_code <= SBI_PMU_FW_RESERVED_MAX) ||
  324. event_code > SBI_PMU_FW_PLATFORM)
  325. return SBI_EINVAL;
  326. if (SBI_PMU_FW_PLATFORM == event_code) {
  327. if (!pmu_dev ||
  328. !pmu_dev->fw_counter_write_value ||
  329. !pmu_dev->fw_counter_start) {
  330. return SBI_EINVAL;
  331. }
  332. if (ival_update)
  333. pmu_dev->fw_counter_write_value(cidx - num_hw_ctrs,
  334. ival);
  335. return pmu_dev->fw_counter_start(cidx - num_hw_ctrs,
  336. event_data);
  337. } else {
  338. if (ival_update)
  339. fw_counters_data[hartid][cidx - num_hw_ctrs] = ival;
  340. }
  341. fw_counters_started[hartid] |= BIT(cidx - num_hw_ctrs);
  342. return 0;
  343. }
  344. int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask,
  345. unsigned long flags, uint64_t ival)
  346. {
  347. u32 hartid = current_hartid();
  348. int event_idx_type;
  349. uint32_t event_code;
  350. int ret = SBI_EINVAL;
  351. bool bUpdate = false;
  352. int i, cidx;
  353. uint64_t edata;
  354. if ((cbase + sbi_fls(cmask)) >= total_ctrs)
  355. return ret;
  356. if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE)
  357. bUpdate = true;
  358. for_each_set_bit(i, &cmask, total_ctrs) {
  359. cidx = i + cbase;
  360. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  361. if (event_idx_type < 0)
  362. /* Continue the start operation for other counters */
  363. continue;
  364. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) {
  365. edata = (event_code == SBI_PMU_FW_PLATFORM) ?
  366. fw_counters_data[hartid][cidx - num_hw_ctrs]
  367. : 0x0;
  368. ret = pmu_ctr_start_fw(cidx, event_code, edata, ival,
  369. bUpdate);
  370. }
  371. else
  372. ret = pmu_ctr_start_hw(cidx, ival, bUpdate);
  373. }
  374. return ret;
  375. }
  376. static int pmu_ctr_stop_hw(uint32_t cidx)
  377. {
  378. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  379. unsigned long mctr_inhbt;
  380. if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
  381. return 0;
  382. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  383. /* Make sure the counter index lies within the range and is not TM bit */
  384. if (cidx >= num_hw_ctrs || cidx == 1)
  385. return SBI_EINVAL;
  386. if (!__test_bit(cidx, &mctr_inhbt)) {
  387. __set_bit(cidx, &mctr_inhbt);
  388. csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt);
  389. return 0;
  390. } else
  391. return SBI_EALREADY_STOPPED;
  392. }
  393. static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t event_code)
  394. {
  395. int ret;
  396. if ((event_code >= SBI_PMU_FW_MAX &&
  397. event_code <= SBI_PMU_FW_RESERVED_MAX) ||
  398. event_code > SBI_PMU_FW_PLATFORM)
  399. return SBI_EINVAL;
  400. if (SBI_PMU_FW_PLATFORM == event_code &&
  401. pmu_dev && pmu_dev->fw_counter_stop) {
  402. ret = pmu_dev->fw_counter_stop(cidx - num_hw_ctrs);
  403. if (ret)
  404. return ret;
  405. }
  406. fw_counters_started[current_hartid()] &= ~BIT(cidx - num_hw_ctrs);
  407. return 0;
  408. }
  409. static int pmu_reset_hw_mhpmevent(int ctr_idx)
  410. {
  411. if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  412. return SBI_EFAIL;
  413. #if __riscv_xlen == 32
  414. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0);
  415. if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
  416. SBI_HART_EXT_SSCOFPMF))
  417. csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, 0);
  418. #else
  419. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0);
  420. #endif
  421. return 0;
  422. }
  423. int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask,
  424. unsigned long flag)
  425. {
  426. u32 hartid = current_hartid();
  427. int ret = SBI_EINVAL;
  428. int event_idx_type;
  429. uint32_t event_code;
  430. int i, cidx;
  431. if ((cbase + sbi_fls(cmask)) >= total_ctrs)
  432. return SBI_EINVAL;
  433. for_each_set_bit(i, &cmask, total_ctrs) {
  434. cidx = i + cbase;
  435. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  436. if (event_idx_type < 0)
  437. /* Continue the stop operation for other counters */
  438. continue;
  439. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
  440. ret = pmu_ctr_stop_fw(cidx, event_code);
  441. else
  442. ret = pmu_ctr_stop_hw(cidx);
  443. if (flag & SBI_PMU_STOP_FLAG_RESET) {
  444. active_events[hartid][cidx] = SBI_PMU_EVENT_IDX_INVALID;
  445. pmu_reset_hw_mhpmevent(cidx);
  446. }
  447. }
  448. return ret;
  449. }
  450. static void pmu_update_inhibit_flags(unsigned long flags, uint64_t *mhpmevent_val)
  451. {
  452. if (flags & SBI_PMU_CFG_FLAG_SET_VUINH)
  453. *mhpmevent_val |= MHPMEVENT_VUINH;
  454. if (flags & SBI_PMU_CFG_FLAG_SET_VSINH)
  455. *mhpmevent_val |= MHPMEVENT_VSINH;
  456. if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
  457. *mhpmevent_val |= MHPMEVENT_UINH;
  458. if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
  459. *mhpmevent_val |= MHPMEVENT_SINH;
  460. }
  461. static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
  462. unsigned long flags, unsigned long eindex,
  463. uint64_t data)
  464. {
  465. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  466. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  467. uint64_t mhpmevent_val;
  468. /* Get the final mhpmevent value to be written from platform */
  469. mhpmevent_val = sbi_platform_pmu_xlate_to_mhpmevent(plat, eindex, data);
  470. if (!mhpmevent_val || ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  471. return SBI_EFAIL;
  472. /**
  473. * Always set the OVF bit(disable interrupts) and inhibit counting of
  474. * events in M-mode. The OVF bit should be enabled during the start call.
  475. */
  476. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  477. mhpmevent_val = (mhpmevent_val & ~MHPMEVENT_SSCOF_MASK) |
  478. MHPMEVENT_MINH | MHPMEVENT_OF;
  479. if (pmu_dev && pmu_dev->hw_counter_disable_irq)
  480. pmu_dev->hw_counter_disable_irq(ctr_idx);
  481. /* Update the inhibit flags based on inhibit flags received from supervisor */
  482. pmu_update_inhibit_flags(flags, &mhpmevent_val);
  483. #if __riscv_xlen == 32
  484. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
  485. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  486. csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3,
  487. mhpmevent_val >> BITS_PER_LONG);
  488. #else
  489. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val);
  490. #endif
  491. return 0;
  492. }
  493. static int pmu_ctr_find_fixed_fw(unsigned long evt_idx_code)
  494. {
  495. /* Non-programmables counters are enabled always. No need to do lookup */
  496. if (evt_idx_code == SBI_PMU_HW_CPU_CYCLES)
  497. return 0;
  498. else if (evt_idx_code == SBI_PMU_HW_INSTRUCTIONS)
  499. return 2;
  500. else
  501. return SBI_EINVAL;
  502. }
  503. static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned long flags,
  504. unsigned long event_idx, uint64_t data)
  505. {
  506. unsigned long ctr_mask;
  507. int i, ret = 0, fixed_ctr, ctr_idx = SBI_ENOTSUPP;
  508. struct sbi_pmu_hw_event *temp;
  509. unsigned long mctr_inhbt = 0;
  510. u32 hartid = current_hartid();
  511. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  512. if (cbase >= num_hw_ctrs)
  513. return SBI_EINVAL;
  514. /**
  515. * If Sscof is present try to find the programmable counter for
  516. * cycle/instret as well.
  517. */
  518. fixed_ctr = pmu_ctr_find_fixed_fw(event_idx);
  519. if (fixed_ctr >= 0 &&
  520. !sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  521. return fixed_ctr;
  522. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11)
  523. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  524. for (i = 0; i < num_hw_events; i++) {
  525. temp = &hw_event_map[i];
  526. if ((temp->start_idx > event_idx && event_idx < temp->end_idx) ||
  527. (temp->start_idx < event_idx && event_idx > temp->end_idx))
  528. continue;
  529. /* For raw events, event data is used as the select value */
  530. if (event_idx == SBI_PMU_EVENT_RAW_IDX) {
  531. uint64_t select_mask = temp->select_mask;
  532. /* The non-event map bits of data should match the selector */
  533. if (temp->select != (data & select_mask))
  534. continue;
  535. }
  536. /* Fixed counters should not be part of the search */
  537. ctr_mask = temp->counters & (cmask << cbase) &
  538. (~SBI_PMU_FIXED_CTR_MASK);
  539. for_each_set_bit_from(cbase, &ctr_mask, SBI_PMU_HW_CTR_MAX) {
  540. /**
  541. * Some of the platform may not support mcountinhibit.
  542. * Checking the active_events is enough for them
  543. */
  544. if (active_events[hartid][cbase] != SBI_PMU_EVENT_IDX_INVALID)
  545. continue;
  546. /* If mcountinhibit is supported, the bit must be enabled */
  547. if ((sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11) &&
  548. !__test_bit(cbase, &mctr_inhbt))
  549. continue;
  550. /* We found a valid counter that is not started yet */
  551. ctr_idx = cbase;
  552. }
  553. }
  554. if (ctr_idx == SBI_ENOTSUPP) {
  555. /**
  556. * We can't find any programmable counters for cycle/instret.
  557. * Return the fixed counter as they are mandatory anyways.
  558. */
  559. if (fixed_ctr >= 0)
  560. return fixed_ctr;
  561. else
  562. return SBI_EFAIL;
  563. }
  564. ret = pmu_update_hw_mhpmevent(temp, ctr_idx, flags, event_idx, data);
  565. if (!ret)
  566. ret = ctr_idx;
  567. return ret;
  568. }
  569. /**
  570. * Any firmware counter can map to any firmware event.
  571. * Thus, select the first available fw counter after sanity
  572. * check.
  573. */
  574. static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask,
  575. uint32_t event_code, u32 hartid, uint64_t edata)
  576. {
  577. int i, cidx;
  578. if ((event_code >= SBI_PMU_FW_MAX &&
  579. event_code <= SBI_PMU_FW_RESERVED_MAX) ||
  580. event_code > SBI_PMU_FW_PLATFORM)
  581. return SBI_EINVAL;
  582. for_each_set_bit(i, &cmask, BITS_PER_LONG) {
  583. cidx = i + cbase;
  584. if (cidx < num_hw_ctrs || total_ctrs <= cidx)
  585. continue;
  586. if (active_events[hartid][i] != SBI_PMU_EVENT_IDX_INVALID)
  587. continue;
  588. if (SBI_PMU_FW_PLATFORM == event_code &&
  589. pmu_dev && pmu_dev->fw_counter_match_encoding) {
  590. if (!pmu_dev->fw_counter_match_encoding(cidx - num_hw_ctrs,
  591. edata))
  592. continue;
  593. }
  594. return i;
  595. }
  596. return SBI_ENOTSUPP;
  597. }
  598. int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
  599. unsigned long flags, unsigned long event_idx,
  600. uint64_t event_data)
  601. {
  602. int ret, ctr_idx = SBI_ENOTSUPP;
  603. u32 event_code, hartid = current_hartid();
  604. int event_type;
  605. /* Do a basic sanity check of counter base & mask */
  606. if ((cidx_base + sbi_fls(cidx_mask)) >= total_ctrs)
  607. return SBI_EINVAL;
  608. event_type = pmu_event_validate(event_idx, event_data);
  609. if (event_type < 0)
  610. return SBI_EINVAL;
  611. event_code = get_cidx_code(event_idx);
  612. if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) {
  613. /* The caller wants to skip the match because it already knows the
  614. * counter idx for the given event. Verify that the counter idx
  615. * is still valid.
  616. */
  617. if (active_events[hartid][cidx_base] == SBI_PMU_EVENT_IDX_INVALID)
  618. return SBI_EINVAL;
  619. ctr_idx = cidx_base;
  620. goto skip_match;
  621. }
  622. if (event_type == SBI_PMU_EVENT_TYPE_FW) {
  623. /* Any firmware counter can be used track any firmware event */
  624. ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code,
  625. hartid, event_data);
  626. if (event_code == SBI_PMU_FW_PLATFORM)
  627. fw_counters_data[hartid][ctr_idx - num_hw_ctrs] =
  628. event_data;
  629. } else {
  630. ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx,
  631. event_data);
  632. }
  633. if (ctr_idx < 0)
  634. return SBI_ENOTSUPP;
  635. active_events[hartid][ctr_idx] = event_idx;
  636. skip_match:
  637. if (event_type == SBI_PMU_EVENT_TYPE_HW) {
  638. if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE)
  639. pmu_ctr_write_hw(ctr_idx, 0);
  640. if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
  641. pmu_ctr_start_hw(ctr_idx, 0, false);
  642. } else if (event_type == SBI_PMU_EVENT_TYPE_FW) {
  643. if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE)
  644. fw_counters_data[hartid][ctr_idx - num_hw_ctrs] = 0;
  645. if (flags & SBI_PMU_CFG_FLAG_AUTO_START) {
  646. if (SBI_PMU_FW_PLATFORM == event_code &&
  647. pmu_dev && pmu_dev->fw_counter_start) {
  648. ret = pmu_dev->fw_counter_start(ctr_idx -
  649. num_hw_ctrs,
  650. event_data);
  651. if (ret)
  652. return ret;
  653. }
  654. fw_counters_started[hartid] |= BIT(ctr_idx - num_hw_ctrs);
  655. }
  656. }
  657. return ctr_idx;
  658. }
  659. int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id)
  660. {
  661. u32 cidx, hartid = current_hartid();
  662. uint64_t *fcounter = NULL;
  663. if (likely(!fw_counters_started[hartid]))
  664. return 0;
  665. if (unlikely(fw_id >= SBI_PMU_FW_MAX))
  666. return SBI_EINVAL;
  667. for (cidx = num_hw_ctrs; cidx < total_ctrs; cidx++) {
  668. if (get_cidx_code(active_events[hartid][cidx]) == fw_id &&
  669. (fw_counters_started[hartid] & BIT(cidx - num_hw_ctrs))) {
  670. fcounter = &fw_counters_data[hartid][cidx - num_hw_ctrs];
  671. break;
  672. }
  673. }
  674. if (fcounter)
  675. (*fcounter)++;
  676. return 0;
  677. }
  678. unsigned long sbi_pmu_num_ctr(void)
  679. {
  680. return (num_hw_ctrs + SBI_PMU_FW_CTR_MAX);
  681. }
  682. int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info)
  683. {
  684. int width;
  685. union sbi_pmu_ctr_info cinfo = {0};
  686. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  687. /* Sanity check. Counter1 is not mapped at all */
  688. if (cidx >= total_ctrs || cidx == 1)
  689. return SBI_EINVAL;
  690. /* We have 31 HW counters with 31 being the last index(MHPMCOUNTER31) */
  691. if (cidx < num_hw_ctrs) {
  692. cinfo.type = SBI_PMU_CTR_TYPE_HW;
  693. cinfo.csr = CSR_CYCLE + cidx;
  694. /* mcycle & minstret are always 64 bit */
  695. if (cidx == 0 || cidx == 2)
  696. cinfo.width = 63;
  697. else
  698. cinfo.width = sbi_hart_mhpm_bits(scratch) - 1;
  699. } else {
  700. /* it's a firmware counter */
  701. cinfo.type = SBI_PMU_CTR_TYPE_FW;
  702. /* Firmware counters are always 64 bits wide */
  703. cinfo.width = 63;
  704. if (pmu_dev && pmu_dev->fw_counter_width) {
  705. width = pmu_dev->fw_counter_width();
  706. if (width)
  707. cinfo.width = width - 1;
  708. }
  709. }
  710. *ctr_info = cinfo.value;
  711. return 0;
  712. }
  713. static void pmu_reset_event_map(u32 hartid)
  714. {
  715. int j;
  716. /* Initialize the counter to event mapping table */
  717. for (j = 3; j < total_ctrs; j++)
  718. active_events[hartid][j] = SBI_PMU_EVENT_IDX_INVALID;
  719. for (j = 0; j < SBI_PMU_FW_CTR_MAX; j++)
  720. fw_counters_data[hartid][j] = 0;
  721. fw_counters_started[hartid] = 0;
  722. }
  723. const struct sbi_pmu_device *sbi_pmu_get_device(void)
  724. {
  725. return pmu_dev;
  726. }
  727. void sbi_pmu_set_device(const struct sbi_pmu_device *dev)
  728. {
  729. if (!dev || pmu_dev)
  730. return;
  731. pmu_dev = dev;
  732. }
  733. void sbi_pmu_exit(struct sbi_scratch *scratch)
  734. {
  735. u32 hartid = current_hartid();
  736. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11)
  737. csr_write(CSR_MCOUNTINHIBIT, 0xFFFFFFF8);
  738. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_10)
  739. csr_write(CSR_MCOUNTEREN, -1);
  740. pmu_reset_event_map(hartid);
  741. }
  742. int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
  743. {
  744. const struct sbi_platform *plat;
  745. u32 hartid = current_hartid();
  746. if (cold_boot) {
  747. plat = sbi_platform_ptr(scratch);
  748. /* Initialize hw pmu events */
  749. sbi_platform_pmu_init(plat);
  750. /* mcycle & minstret is available always */
  751. num_hw_ctrs = sbi_hart_mhpm_count(scratch) + 3;
  752. total_ctrs = num_hw_ctrs + SBI_PMU_FW_CTR_MAX;
  753. }
  754. pmu_reset_event_map(hartid);
  755. /* First three counters are fixed by the priv spec and we enable it by default */
  756. active_events[hartid][0] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET |
  757. SBI_PMU_HW_CPU_CYCLES;
  758. active_events[hartid][1] = SBI_PMU_EVENT_IDX_INVALID;
  759. active_events[hartid][2] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET |
  760. SBI_PMU_HW_INSTRUCTIONS;
  761. return 0;
  762. }