sbi_ecall_interface.h 8.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272
  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #ifndef __SBI_ECALL_INTERFACE_H__
  10. #define __SBI_ECALL_INTERFACE_H__
  11. /* clang-format off */
  12. /* SBI Extension IDs */
  13. #define SBI_EXT_0_1_SET_TIMER 0x0
  14. #define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
  15. #define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
  16. #define SBI_EXT_0_1_CLEAR_IPI 0x3
  17. #define SBI_EXT_0_1_SEND_IPI 0x4
  18. #define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
  19. #define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
  20. #define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
  21. #define SBI_EXT_0_1_SHUTDOWN 0x8
  22. #define SBI_EXT_BASE 0x10
  23. #define SBI_EXT_TIME 0x54494D45
  24. #define SBI_EXT_IPI 0x735049
  25. #define SBI_EXT_RFENCE 0x52464E43
  26. #define SBI_EXT_HSM 0x48534D
  27. #define SBI_EXT_SRST 0x53525354
  28. #define SBI_EXT_PMU 0x504D55
  29. #define SBI_EXT_DBCN 0x4442434E
  30. #define SBI_EXT_SUSP 0x53555350
  31. /* SBI function IDs for BASE extension*/
  32. #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
  33. #define SBI_EXT_BASE_GET_IMP_ID 0x1
  34. #define SBI_EXT_BASE_GET_IMP_VERSION 0x2
  35. #define SBI_EXT_BASE_PROBE_EXT 0x3
  36. #define SBI_EXT_BASE_GET_MVENDORID 0x4
  37. #define SBI_EXT_BASE_GET_MARCHID 0x5
  38. #define SBI_EXT_BASE_GET_MIMPID 0x6
  39. /* SBI function IDs for TIME extension*/
  40. #define SBI_EXT_TIME_SET_TIMER 0x0
  41. /* SBI function IDs for IPI extension*/
  42. #define SBI_EXT_IPI_SEND_IPI 0x0
  43. /* SBI function IDs for RFENCE extension*/
  44. #define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
  45. #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1
  46. #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2
  47. #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x3
  48. #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x4
  49. #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x5
  50. #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x6
  51. /* SBI function IDs for HSM extension */
  52. #define SBI_EXT_HSM_HART_START 0x0
  53. #define SBI_EXT_HSM_HART_STOP 0x1
  54. #define SBI_EXT_HSM_HART_GET_STATUS 0x2
  55. #define SBI_EXT_HSM_HART_SUSPEND 0x3
  56. #define SBI_HSM_STATE_STARTED 0x0
  57. #define SBI_HSM_STATE_STOPPED 0x1
  58. #define SBI_HSM_STATE_START_PENDING 0x2
  59. #define SBI_HSM_STATE_STOP_PENDING 0x3
  60. #define SBI_HSM_STATE_SUSPENDED 0x4
  61. #define SBI_HSM_STATE_SUSPEND_PENDING 0x5
  62. #define SBI_HSM_STATE_RESUME_PENDING 0x6
  63. #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
  64. #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
  65. #define SBI_HSM_SUSP_PLAT_BASE 0x10000000
  66. #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
  67. #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
  68. #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
  69. #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
  70. #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
  71. SBI_HSM_SUSP_PLAT_BASE)
  72. #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
  73. SBI_HSM_SUSP_BASE_MASK)
  74. /* SBI function IDs for SRST extension */
  75. #define SBI_EXT_SRST_RESET 0x0
  76. #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
  77. #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
  78. #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
  79. #define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT
  80. #define SBI_SRST_RESET_REASON_NONE 0x0
  81. #define SBI_SRST_RESET_REASON_SYSFAIL 0x1
  82. /* SBI function IDs for PMU extension */
  83. #define SBI_EXT_PMU_NUM_COUNTERS 0x0
  84. #define SBI_EXT_PMU_COUNTER_GET_INFO 0x1
  85. #define SBI_EXT_PMU_COUNTER_CFG_MATCH 0x2
  86. #define SBI_EXT_PMU_COUNTER_START 0x3
  87. #define SBI_EXT_PMU_COUNTER_STOP 0x4
  88. #define SBI_EXT_PMU_COUNTER_FW_READ 0x5
  89. #define SBI_EXT_PMU_COUNTER_FW_READ_HI 0x6
  90. /** General pmu event codes specified in SBI PMU extension */
  91. enum sbi_pmu_hw_generic_events_t {
  92. SBI_PMU_HW_NO_EVENT = 0,
  93. SBI_PMU_HW_CPU_CYCLES = 1,
  94. SBI_PMU_HW_INSTRUCTIONS = 2,
  95. SBI_PMU_HW_CACHE_REFERENCES = 3,
  96. SBI_PMU_HW_CACHE_MISSES = 4,
  97. SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
  98. SBI_PMU_HW_BRANCH_MISSES = 6,
  99. SBI_PMU_HW_BUS_CYCLES = 7,
  100. SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
  101. SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
  102. SBI_PMU_HW_REF_CPU_CYCLES = 10,
  103. SBI_PMU_HW_GENERAL_MAX,
  104. };
  105. /**
  106. * Generalized hardware cache events:
  107. *
  108. * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
  109. * { read, write, prefetch } x
  110. * { accesses, misses }
  111. */
  112. enum sbi_pmu_hw_cache_id {
  113. SBI_PMU_HW_CACHE_L1D = 0,
  114. SBI_PMU_HW_CACHE_L1I = 1,
  115. SBI_PMU_HW_CACHE_LL = 2,
  116. SBI_PMU_HW_CACHE_DTLB = 3,
  117. SBI_PMU_HW_CACHE_ITLB = 4,
  118. SBI_PMU_HW_CACHE_BPU = 5,
  119. SBI_PMU_HW_CACHE_NODE = 6,
  120. SBI_PMU_HW_CACHE_MAX,
  121. };
  122. enum sbi_pmu_hw_cache_op_id {
  123. SBI_PMU_HW_CACHE_OP_READ = 0,
  124. SBI_PMU_HW_CACHE_OP_WRITE = 1,
  125. SBI_PMU_HW_CACHE_OP_PREFETCH = 2,
  126. SBI_PMU_HW_CACHE_OP_MAX,
  127. };
  128. enum sbi_pmu_hw_cache_op_result_id {
  129. SBI_PMU_HW_CACHE_RESULT_ACCESS = 0,
  130. SBI_PMU_HW_CACHE_RESULT_MISS = 1,
  131. SBI_PMU_HW_CACHE_RESULT_MAX,
  132. };
  133. /**
  134. * Special "firmware" events provided by the OpenSBI, even if the hardware
  135. * does not support performance events. These events are encoded as a raw
  136. * event type in Linux kernel perf framework.
  137. */
  138. enum sbi_pmu_fw_event_code_id {
  139. SBI_PMU_FW_MISALIGNED_LOAD = 0,
  140. SBI_PMU_FW_MISALIGNED_STORE = 1,
  141. SBI_PMU_FW_ACCESS_LOAD = 2,
  142. SBI_PMU_FW_ACCESS_STORE = 3,
  143. SBI_PMU_FW_ILLEGAL_INSN = 4,
  144. SBI_PMU_FW_SET_TIMER = 5,
  145. SBI_PMU_FW_IPI_SENT = 6,
  146. SBI_PMU_FW_IPI_RECVD = 7,
  147. SBI_PMU_FW_FENCE_I_SENT = 8,
  148. SBI_PMU_FW_FENCE_I_RECVD = 9,
  149. SBI_PMU_FW_SFENCE_VMA_SENT = 10,
  150. SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
  151. SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
  152. SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
  153. SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
  154. SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
  155. SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
  156. SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
  157. SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
  158. SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
  159. SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
  160. SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
  161. SBI_PMU_FW_MAX,
  162. };
  163. /** SBI PMU event idx type */
  164. enum sbi_pmu_event_type_id {
  165. SBI_PMU_EVENT_TYPE_HW = 0x0,
  166. SBI_PMU_EVENT_TYPE_HW_CACHE = 0x1,
  167. SBI_PMU_EVENT_TYPE_HW_RAW = 0x2,
  168. SBI_PMU_EVENT_TYPE_FW = 0xf,
  169. SBI_PMU_EVENT_TYPE_MAX,
  170. };
  171. /** SBI PMU counter type */
  172. enum sbi_pmu_ctr_type {
  173. SBI_PMU_CTR_TYPE_HW = 0,
  174. SBI_PMU_CTR_TYPE_FW,
  175. };
  176. /* Helper macros to decode event idx */
  177. #define SBI_PMU_EVENT_IDX_OFFSET 20
  178. #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
  179. #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
  180. #define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
  181. #define SBI_PMU_EVENT_RAW_IDX 0x20000
  182. #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
  183. #define SBI_PMU_EVENT_HW_CACHE_OPS_RESULT 0x1
  184. #define SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK 0x6
  185. #define SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET 1
  186. #define SBI_PMU_EVENT_HW_CACHE_ID_MASK 0xfff8
  187. #define SBI_PMU_EVENT_HW_CACHE_ID_OFFSET 3
  188. /* Flags defined for config matching function */
  189. #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0)
  190. #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1)
  191. #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2)
  192. #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3)
  193. #define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4)
  194. #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5)
  195. #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6)
  196. #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7)
  197. /* Flags defined for counter start function */
  198. #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
  199. /* Flags defined for counter stop function */
  200. #define SBI_PMU_STOP_FLAG_RESET (1 << 0)
  201. /* SBI function IDs for DBCN extension */
  202. #define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
  203. #define SBI_EXT_DBCN_CONSOLE_READ 0x1
  204. #define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
  205. /* SBI function IDs for SUSP extension */
  206. #define SBI_EXT_SUSP_SUSPEND 0x0
  207. #define SBI_SUSP_SLEEP_TYPE_SUSPEND 0x0
  208. #define SBI_SUSP_SLEEP_TYPE_LAST SBI_SUSP_SLEEP_TYPE_SUSPEND
  209. #define SBI_SUSP_PLATFORM_SLEEP_START 0x80000000
  210. /* SBI base specification related macros */
  211. #define SBI_SPEC_VERSION_MAJOR_OFFSET 24
  212. #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
  213. #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
  214. #define SBI_EXT_VENDOR_START 0x09000000
  215. #define SBI_EXT_VENDOR_END 0x09FFFFFF
  216. #define SBI_EXT_FIRMWARE_START 0x0A000000
  217. #define SBI_EXT_FIRMWARE_END 0x0AFFFFFF
  218. /* SBI return error codes */
  219. #define SBI_SUCCESS 0
  220. #define SBI_ERR_FAILED -1
  221. #define SBI_ERR_NOT_SUPPORTED -2
  222. #define SBI_ERR_INVALID_PARAM -3
  223. #define SBI_ERR_DENIED -4
  224. #define SBI_ERR_INVALID_ADDRESS -5
  225. #define SBI_ERR_ALREADY_AVAILABLE -6
  226. #define SBI_ERR_ALREADY_STARTED -7
  227. #define SBI_ERR_ALREADY_STOPPED -8
  228. #define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED
  229. /* clang-format on */
  230. #endif