sbi_pmu.h 3.8 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #ifndef __SBI_PMU_H__
  10. #define __SBI_PMU_H__
  11. #include <sbi/sbi_types.h>
  12. struct sbi_scratch;
  13. /* Event related macros */
  14. /* Maximum number of hardware events that can mapped by OpenSBI */
  15. #define SBI_PMU_HW_EVENT_MAX 256
  16. /* Counter related macros */
  17. #define SBI_PMU_FW_CTR_MAX 16
  18. #define SBI_PMU_HW_CTR_MAX 32
  19. #define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX)
  20. #define SBI_PMU_FIXED_CTR_MASK 0x07
  21. struct sbi_pmu_device {
  22. /** Name of the PMU platform device */
  23. char name[32];
  24. /**
  25. * Validate event code of custom firmware event
  26. * Note: SBI_PMU_FW_MAX <= event_idx_code
  27. */
  28. int (*fw_event_validate_code)(uint32_t event_idx_code);
  29. /**
  30. * Match custom firmware counter with custom firmware event
  31. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  32. */
  33. bool (*fw_counter_match_code)(uint32_t counter_index,
  34. uint32_t event_idx_code);
  35. /**
  36. * Read value of custom firmware counter
  37. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  38. */
  39. uint64_t (*fw_counter_read_value)(uint32_t counter_index);
  40. /**
  41. * Start custom firmware counter
  42. * Note: SBI_PMU_FW_MAX <= event_idx_code
  43. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  44. */
  45. int (*fw_counter_start)(uint32_t counter_index,
  46. uint32_t event_idx_code,
  47. uint64_t init_val, bool init_val_update);
  48. /**
  49. * Stop custom firmware counter
  50. * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
  51. */
  52. int (*fw_counter_stop)(uint32_t counter_index);
  53. /**
  54. * Custom enable irq for hardware counter
  55. * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
  56. */
  57. void (*hw_counter_enable_irq)(uint32_t counter_index);
  58. /**
  59. * Custom disable irq for hardware counter
  60. * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
  61. */
  62. void (*hw_counter_disable_irq)(uint32_t counter_index);
  63. /**
  64. * Custom function returning the machine-specific irq-bit.
  65. */
  66. int (*hw_counter_irq_bit)(void);
  67. };
  68. /** Get the PMU platform device */
  69. const struct sbi_pmu_device *sbi_pmu_get_device(void);
  70. /** Set the PMU platform device */
  71. void sbi_pmu_set_device(const struct sbi_pmu_device *dev);
  72. /** Initialize PMU */
  73. int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
  74. /** Reset PMU during hart exit */
  75. void sbi_pmu_exit(struct sbi_scratch *scratch);
  76. /** Return the pmu irq bit depending on extension existence */
  77. int sbi_pmu_irq_bit(void);
  78. /**
  79. * Add the hardware event to counter mapping information. This should be called
  80. * from the platform code to update the mapping table.
  81. * @param eidx_start Start of the event idx range for supported counters
  82. * @param eidx_end End of the event idx range for supported counters
  83. * @param cmap A bitmap representing counters supporting the event range
  84. * @return 0 on success, error otherwise.
  85. */
  86. int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap);
  87. /**
  88. * Add the raw hardware event selector and supported counter information. This
  89. * should be called from the platform code to update the mapping table.
  90. * @param info a pointer to the hardware event info
  91. * @return 0 on success, error otherwise.
  92. */
  93. int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap);
  94. int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval);
  95. int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask,
  96. unsigned long flag);
  97. int sbi_pmu_ctr_start(unsigned long cidx_base, unsigned long cidx_mask,
  98. unsigned long flags, uint64_t ival);
  99. int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info);
  100. unsigned long sbi_pmu_num_ctr(void);
  101. int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
  102. unsigned long flags, unsigned long event_idx,
  103. uint64_t event_data);
  104. int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id);
  105. #endif