sbi_pmu.c 23 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/sbi_bitops.h>
  11. #include <sbi/sbi_console.h>
  12. #include <sbi/sbi_ecall_interface.h>
  13. #include <sbi/sbi_hart.h>
  14. #include <sbi/sbi_hartmask.h>
  15. #include <sbi/sbi_platform.h>
  16. #include <sbi/sbi_pmu.h>
  17. #include <sbi/sbi_scratch.h>
  18. #include <sbi/sbi_string.h>
  19. /** Information about hardware counters */
  20. struct sbi_pmu_hw_event {
  21. uint32_t counters;
  22. uint32_t start_idx;
  23. uint32_t end_idx;
  24. /* Event selector value used only for raw events. The event select value
  25. * can be a even id or a selector value for set of events encoded in few
  26. * bits. In case latter, the bits used for encoding of the events should
  27. * be zeroed out in the select value.
  28. */
  29. uint64_t select;
  30. /**
  31. * The select_mask indicates which bits are encoded for the event(s).
  32. */
  33. uint64_t select_mask;
  34. };
  35. /* Information about PMU counters as per SBI specification */
  36. union sbi_pmu_ctr_info {
  37. unsigned long value;
  38. struct {
  39. unsigned long csr:12;
  40. unsigned long width:6;
  41. #if __riscv_xlen == 32
  42. unsigned long reserved:13;
  43. #else
  44. unsigned long reserved:45;
  45. #endif
  46. unsigned long type:1;
  47. };
  48. };
  49. /* Platform specific PMU device */
  50. static const struct sbi_pmu_device *pmu_dev = NULL;
  51. /* Mapping between event range and possible counters */
  52. static struct sbi_pmu_hw_event hw_event_map[SBI_PMU_HW_EVENT_MAX] = {0};
  53. /* counter to enabled event mapping */
  54. static uint32_t active_events[SBI_HARTMASK_MAX_BITS][SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX];
  55. /* Bitmap of firmware counters started on each HART */
  56. #if SBI_PMU_FW_CTR_MAX >= BITS_PER_LONG
  57. #error "Can't handle firmware counters beyond BITS_PER_LONG"
  58. #endif
  59. static unsigned long fw_counters_started[SBI_HARTMASK_MAX_BITS];
  60. /* Values of firmwares counters on each HART */
  61. static uint64_t fw_counters_value[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_CTR_MAX] = {0};
  62. /* Maximum number of hardware events available */
  63. static uint32_t num_hw_events;
  64. /* Maximum number of hardware counters available */
  65. static uint32_t num_hw_ctrs;
  66. /* Maximum number of counters available */
  67. static uint32_t total_ctrs;
  68. /* Helper macros to retrieve event idx and code type */
  69. #define get_cidx_type(x) ((x & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16)
  70. #define get_cidx_code(x) (x & SBI_PMU_EVENT_IDX_CODE_MASK)
  71. /**
  72. * Perform a sanity check on event & counter mappings with event range overlap check
  73. * @param evtA Pointer to the existing hw event structure
  74. * @param evtB Pointer to the new hw event structure
  75. *
  76. * Return false if the range doesn't overlap, true otherwise
  77. */
  78. static bool pmu_event_range_overlap(struct sbi_pmu_hw_event *evtA,
  79. struct sbi_pmu_hw_event *evtB)
  80. {
  81. /* check if the range of events overlap with a previous entry */
  82. if (((evtA->end_idx < evtB->start_idx) && (evtA->end_idx < evtB->end_idx)) ||
  83. ((evtA->start_idx > evtB->start_idx) && (evtA->start_idx > evtB->end_idx)))
  84. return false;
  85. return true;
  86. }
  87. static bool pmu_event_select_overlap(struct sbi_pmu_hw_event *evt,
  88. uint64_t select_val, uint64_t select_mask)
  89. {
  90. if ((evt->select == select_val) && (evt->select_mask == select_mask))
  91. return true;
  92. return false;
  93. }
  94. static int pmu_event_validate(unsigned long event_idx)
  95. {
  96. uint32_t event_idx_type = get_cidx_type(event_idx);
  97. uint32_t event_idx_code = get_cidx_code(event_idx);
  98. uint32_t event_idx_code_max = -1;
  99. uint32_t cache_ops_result, cache_ops_id, cache_id;
  100. switch(event_idx_type) {
  101. case SBI_PMU_EVENT_TYPE_HW:
  102. event_idx_code_max = SBI_PMU_HW_GENERAL_MAX;
  103. break;
  104. case SBI_PMU_EVENT_TYPE_FW:
  105. if (SBI_PMU_FW_MAX <= event_idx_code &&
  106. pmu_dev && pmu_dev->fw_event_validate_code)
  107. return pmu_dev->fw_event_validate_code(event_idx_code);
  108. else
  109. event_idx_code_max = SBI_PMU_FW_MAX;
  110. break;
  111. case SBI_PMU_EVENT_TYPE_HW_CACHE:
  112. cache_ops_result = event_idx_code &
  113. SBI_PMU_EVENT_HW_CACHE_OPS_RESULT;
  114. cache_ops_id = (event_idx_code &
  115. SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK) >>
  116. SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET;
  117. cache_id = (event_idx_code &
  118. SBI_PMU_EVENT_HW_CACHE_ID_MASK) >>
  119. SBI_PMU_EVENT_HW_CACHE_ID_OFFSET;
  120. if ((cache_ops_result < SBI_PMU_HW_CACHE_RESULT_MAX) &&
  121. (cache_ops_id < SBI_PMU_HW_CACHE_OP_MAX) &&
  122. (cache_id < SBI_PMU_HW_CACHE_MAX))
  123. return event_idx_type;
  124. else
  125. return SBI_EINVAL;
  126. break;
  127. case SBI_PMU_EVENT_TYPE_HW_RAW:
  128. event_idx_code_max = 1; // event_idx.code should be zero
  129. break;
  130. default:
  131. return SBI_EINVAL;
  132. }
  133. if (event_idx_code < event_idx_code_max)
  134. return event_idx_type;
  135. return SBI_EINVAL;
  136. }
  137. static int pmu_ctr_validate(uint32_t cidx, uint32_t *event_idx_code)
  138. {
  139. uint32_t event_idx_val;
  140. uint32_t event_idx_type;
  141. u32 hartid = current_hartid();
  142. if (cidx >= total_ctrs)
  143. return SBI_EINVAL;
  144. event_idx_val = active_events[hartid][cidx];
  145. event_idx_type = get_cidx_type(event_idx_val);
  146. if (event_idx_val == SBI_PMU_EVENT_IDX_INVALID ||
  147. event_idx_type >= SBI_PMU_EVENT_TYPE_MAX)
  148. return SBI_EINVAL;
  149. *event_idx_code = get_cidx_code(event_idx_val);
  150. return event_idx_type;
  151. }
  152. int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval)
  153. {
  154. int event_idx_type;
  155. uint32_t event_code;
  156. u32 hartid = current_hartid();
  157. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  158. if (event_idx_type != SBI_PMU_EVENT_TYPE_FW)
  159. return SBI_EINVAL;
  160. if (SBI_PMU_FW_MAX <= event_code &&
  161. pmu_dev && pmu_dev->fw_counter_read_value)
  162. fw_counters_value[hartid][cidx - num_hw_ctrs] =
  163. pmu_dev->fw_counter_read_value(cidx - num_hw_ctrs);
  164. *cval = fw_counters_value[hartid][cidx - num_hw_ctrs];
  165. return 0;
  166. }
  167. static int pmu_add_hw_event_map(u32 eidx_start, u32 eidx_end, u32 cmap,
  168. uint64_t select, uint64_t select_mask)
  169. {
  170. int i = 0;
  171. bool is_overlap;
  172. struct sbi_pmu_hw_event *event = &hw_event_map[num_hw_events];
  173. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  174. int hw_ctr_avail = sbi_hart_mhpm_count(scratch);
  175. uint32_t ctr_avail_mask = ((uint32_t)(~0) >> (32 - (hw_ctr_avail + 3)));
  176. /* The first two counters are reserved by priv spec */
  177. if (eidx_start > SBI_PMU_HW_INSTRUCTIONS && (cmap & SBI_PMU_FIXED_CTR_MASK))
  178. return SBI_EDENIED;
  179. if (num_hw_events >= SBI_PMU_HW_EVENT_MAX - 1) {
  180. sbi_printf("Can not handle more than %d perf events\n",
  181. SBI_PMU_HW_EVENT_MAX);
  182. return SBI_EFAIL;
  183. }
  184. event->start_idx = eidx_start;
  185. event->end_idx = eidx_end;
  186. /* Sanity check */
  187. for (i = 0; i < num_hw_events; i++) {
  188. if (eidx_start == SBI_PMU_EVENT_RAW_IDX)
  189. /* All raw events have same event idx. Just do sanity check on select */
  190. is_overlap = pmu_event_select_overlap(&hw_event_map[i],
  191. select, select_mask);
  192. else
  193. is_overlap = pmu_event_range_overlap(&hw_event_map[i], event);
  194. if (is_overlap)
  195. goto reset_event;
  196. }
  197. event->select_mask = select_mask;
  198. /* Map the only the counters that are available in the hardware */
  199. event->counters = cmap & ctr_avail_mask;
  200. event->select = select;
  201. num_hw_events++;
  202. return 0;
  203. reset_event:
  204. event->start_idx = 0;
  205. event->end_idx = 0;
  206. return SBI_EINVAL;
  207. }
  208. /**
  209. * Logical counter ids are assigned to hardware counters are assigned consecutively.
  210. * E.g. counter0 must count MCYCLE where counter2 must count minstret. Similarly,
  211. * counterX will mhpmcounterX.
  212. */
  213. int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap)
  214. {
  215. if ((eidx_start > eidx_end) || eidx_start == SBI_PMU_EVENT_RAW_IDX ||
  216. eidx_end == SBI_PMU_EVENT_RAW_IDX)
  217. return SBI_EINVAL;
  218. return pmu_add_hw_event_map(eidx_start, eidx_end, cmap, 0, 0);
  219. }
  220. int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap)
  221. {
  222. return pmu_add_hw_event_map(SBI_PMU_EVENT_RAW_IDX,
  223. SBI_PMU_EVENT_RAW_IDX, cmap, select, select_mask);
  224. }
  225. static int pmu_ctr_enable_irq_hw(int ctr_idx)
  226. {
  227. unsigned long mhpmevent_csr;
  228. unsigned long mhpmevent_curr;
  229. unsigned long mip_val;
  230. unsigned long of_mask;
  231. if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  232. return SBI_EFAIL;
  233. #if __riscv_xlen == 32
  234. mhpmevent_csr = CSR_MHPMEVENT3H + ctr_idx - 3;
  235. of_mask = (uint32_t)~MHPMEVENTH_OF;
  236. #else
  237. mhpmevent_csr = CSR_MHPMEVENT3 + ctr_idx - 3;
  238. of_mask = ~MHPMEVENT_OF;
  239. #endif
  240. mhpmevent_curr = csr_read_num(mhpmevent_csr);
  241. mip_val = csr_read(CSR_MIP);
  242. /**
  243. * Clear out the OF bit so that next interrupt can be enabled.
  244. * This should be done only when the corresponding overflow interrupt
  245. * bit is cleared. That indicates that software has already handled the
  246. * previous interrupts or the hardware yet to set an overflow interrupt.
  247. * Otherwise, there will be race conditions where we may clear the bit
  248. * the software is yet to handle the interrupt.
  249. */
  250. if (!(mip_val & MIP_LCOFIP)) {
  251. mhpmevent_curr &= of_mask;
  252. csr_write_num(mhpmevent_csr, mhpmevent_curr);
  253. }
  254. return 0;
  255. }
  256. static void pmu_ctr_write_hw(uint32_t cidx, uint64_t ival)
  257. {
  258. #if __riscv_xlen == 32
  259. csr_write_num(CSR_MCYCLE + cidx, 0);
  260. csr_write_num(CSR_MCYCLE + cidx, ival & 0xFFFFFFFF);
  261. csr_write_num(CSR_MCYCLEH + cidx, ival >> BITS_PER_LONG);
  262. #else
  263. csr_write_num(CSR_MCYCLE + cidx, ival);
  264. #endif
  265. }
  266. static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
  267. {
  268. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  269. unsigned long mctr_inhbt;
  270. /* Make sure the counter index lies within the range and is not TM bit */
  271. if (cidx >= num_hw_ctrs || cidx == 1)
  272. return SBI_EINVAL;
  273. if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
  274. goto skip_inhibit_update;
  275. /*
  276. * Some of the hardware may not support mcountinhibit but perf stat
  277. * still can work if supervisor mode programs the initial value.
  278. */
  279. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  280. if (!__test_bit(cidx, &mctr_inhbt))
  281. return SBI_EALREADY_STARTED;
  282. __clear_bit(cidx, &mctr_inhbt);
  283. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  284. pmu_ctr_enable_irq_hw(cidx);
  285. if (pmu_dev && pmu_dev->hw_counter_enable_irq)
  286. pmu_dev->hw_counter_enable_irq(cidx);
  287. csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt);
  288. skip_inhibit_update:
  289. if (ival_update)
  290. pmu_ctr_write_hw(cidx, ival);
  291. return 0;
  292. }
  293. int sbi_pmu_irq_bit(void)
  294. {
  295. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  296. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  297. return MIP_LCOFIP;
  298. if (pmu_dev && pmu_dev->hw_counter_irq_bit)
  299. return pmu_dev->hw_counter_irq_bit();
  300. return 0;
  301. }
  302. static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code,
  303. uint64_t ival, bool ival_update)
  304. {
  305. int ret;
  306. u32 hartid = current_hartid();
  307. if (SBI_PMU_FW_MAX <= event_code &&
  308. pmu_dev && pmu_dev->fw_counter_start) {
  309. ret = pmu_dev->fw_counter_start(cidx - num_hw_ctrs,
  310. event_code,
  311. ival, ival_update);
  312. if (ret)
  313. return ret;
  314. }
  315. if (ival_update)
  316. fw_counters_value[hartid][cidx - num_hw_ctrs] = ival;
  317. fw_counters_started[hartid] |= BIT(cidx - num_hw_ctrs);
  318. return 0;
  319. }
  320. int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask,
  321. unsigned long flags, uint64_t ival)
  322. {
  323. int event_idx_type;
  324. uint32_t event_code;
  325. int ret = SBI_EINVAL;
  326. bool bUpdate = false;
  327. int i, cidx;
  328. if ((cbase + sbi_fls(cmask)) >= total_ctrs)
  329. return ret;
  330. if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE)
  331. bUpdate = true;
  332. for_each_set_bit(i, &cmask, total_ctrs) {
  333. cidx = i + cbase;
  334. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  335. if (event_idx_type < 0)
  336. /* Continue the start operation for other counters */
  337. continue;
  338. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
  339. ret = pmu_ctr_start_fw(cidx, event_code, ival, bUpdate);
  340. else
  341. ret = pmu_ctr_start_hw(cidx, ival, bUpdate);
  342. }
  343. return ret;
  344. }
  345. static int pmu_ctr_stop_hw(uint32_t cidx)
  346. {
  347. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  348. unsigned long mctr_inhbt;
  349. if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
  350. return 0;
  351. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  352. /* Make sure the counter index lies within the range and is not TM bit */
  353. if (cidx >= num_hw_ctrs || cidx == 1)
  354. return SBI_EINVAL;
  355. if (!__test_bit(cidx, &mctr_inhbt)) {
  356. __set_bit(cidx, &mctr_inhbt);
  357. csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt);
  358. return 0;
  359. } else
  360. return SBI_EALREADY_STOPPED;
  361. }
  362. static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t event_code)
  363. {
  364. int ret;
  365. if (SBI_PMU_FW_MAX <= event_code &&
  366. pmu_dev && pmu_dev->fw_counter_stop) {
  367. ret = pmu_dev->fw_counter_stop(cidx - num_hw_ctrs);
  368. if (ret)
  369. return ret;
  370. }
  371. fw_counters_started[current_hartid()] &= ~BIT(cidx - num_hw_ctrs);
  372. return 0;
  373. }
  374. static int pmu_reset_hw_mhpmevent(int ctr_idx)
  375. {
  376. if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  377. return SBI_EFAIL;
  378. #if __riscv_xlen == 32
  379. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0);
  380. if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
  381. SBI_HART_EXT_SSCOFPMF))
  382. csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, 0);
  383. #else
  384. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0);
  385. #endif
  386. return 0;
  387. }
  388. int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask,
  389. unsigned long flag)
  390. {
  391. u32 hartid = current_hartid();
  392. int ret = SBI_EINVAL;
  393. int event_idx_type;
  394. uint32_t event_code;
  395. int i, cidx;
  396. if ((cbase + sbi_fls(cmask)) >= total_ctrs)
  397. return SBI_EINVAL;
  398. for_each_set_bit(i, &cmask, total_ctrs) {
  399. cidx = i + cbase;
  400. event_idx_type = pmu_ctr_validate(cidx, &event_code);
  401. if (event_idx_type < 0)
  402. /* Continue the stop operation for other counters */
  403. continue;
  404. else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
  405. ret = pmu_ctr_stop_fw(cidx, event_code);
  406. else
  407. ret = pmu_ctr_stop_hw(cidx);
  408. if (flag & SBI_PMU_STOP_FLAG_RESET) {
  409. active_events[hartid][cidx] = SBI_PMU_EVENT_IDX_INVALID;
  410. pmu_reset_hw_mhpmevent(cidx);
  411. }
  412. }
  413. return ret;
  414. }
  415. static void pmu_update_inhibit_flags(unsigned long flags, uint64_t *mhpmevent_val)
  416. {
  417. if (flags & SBI_PMU_CFG_FLAG_SET_VUINH)
  418. *mhpmevent_val |= MHPMEVENT_VUINH;
  419. if (flags & SBI_PMU_CFG_FLAG_SET_VSINH)
  420. *mhpmevent_val |= MHPMEVENT_VSINH;
  421. if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
  422. *mhpmevent_val |= MHPMEVENT_UINH;
  423. if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
  424. *mhpmevent_val |= MHPMEVENT_SINH;
  425. }
  426. static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
  427. unsigned long flags, unsigned long eindex,
  428. uint64_t data)
  429. {
  430. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  431. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  432. uint64_t mhpmevent_val;
  433. /* Get the final mhpmevent value to be written from platform */
  434. mhpmevent_val = sbi_platform_pmu_xlate_to_mhpmevent(plat, eindex, data);
  435. if (!mhpmevent_val || ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX)
  436. return SBI_EFAIL;
  437. /**
  438. * Always set the OVF bit(disable interrupts) and inhibit counting of
  439. * events in M-mode. The OVF bit should be enabled during the start call.
  440. */
  441. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  442. mhpmevent_val = (mhpmevent_val & ~MHPMEVENT_SSCOF_MASK) |
  443. MHPMEVENT_MINH | MHPMEVENT_OF;
  444. if (pmu_dev && pmu_dev->hw_counter_disable_irq)
  445. pmu_dev->hw_counter_disable_irq(ctr_idx);
  446. /* Update the inhibit flags based on inhibit flags received from supervisor */
  447. pmu_update_inhibit_flags(flags, &mhpmevent_val);
  448. #if __riscv_xlen == 32
  449. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
  450. if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  451. csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3,
  452. mhpmevent_val >> BITS_PER_LONG);
  453. #else
  454. csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val);
  455. #endif
  456. return 0;
  457. }
  458. static int pmu_ctr_find_fixed_fw(unsigned long evt_idx_code)
  459. {
  460. /* Non-programmables counters are enabled always. No need to do lookup */
  461. if (evt_idx_code == SBI_PMU_HW_CPU_CYCLES)
  462. return 0;
  463. else if (evt_idx_code == SBI_PMU_HW_INSTRUCTIONS)
  464. return 2;
  465. else
  466. return SBI_EINVAL;
  467. }
  468. static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned long flags,
  469. unsigned long event_idx, uint64_t data)
  470. {
  471. unsigned long ctr_mask;
  472. int i, ret = 0, fixed_ctr, ctr_idx = SBI_ENOTSUPP;
  473. struct sbi_pmu_hw_event *temp;
  474. unsigned long mctr_inhbt = 0;
  475. u32 hartid = current_hartid();
  476. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  477. if (cbase >= num_hw_ctrs)
  478. return SBI_EINVAL;
  479. /**
  480. * If Sscof is present try to find the programmable counter for
  481. * cycle/instret as well.
  482. */
  483. fixed_ctr = pmu_ctr_find_fixed_fw(event_idx);
  484. if (fixed_ctr >= 0 &&
  485. !sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
  486. return fixed_ctr;
  487. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11)
  488. mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
  489. for (i = 0; i < num_hw_events; i++) {
  490. temp = &hw_event_map[i];
  491. if ((temp->start_idx > event_idx && event_idx < temp->end_idx) ||
  492. (temp->start_idx < event_idx && event_idx > temp->end_idx))
  493. continue;
  494. /* For raw events, event data is used as the select value */
  495. if (event_idx == SBI_PMU_EVENT_RAW_IDX) {
  496. uint64_t select_mask = temp->select_mask;
  497. /* The non-event map bits of data should match the selector */
  498. if (temp->select != (data & select_mask))
  499. continue;
  500. }
  501. /* Fixed counters should not be part of the search */
  502. ctr_mask = temp->counters & (cmask << cbase) &
  503. (~SBI_PMU_FIXED_CTR_MASK);
  504. for_each_set_bit_from(cbase, &ctr_mask, SBI_PMU_HW_CTR_MAX) {
  505. /**
  506. * Some of the platform may not support mcountinhibit.
  507. * Checking the active_events is enough for them
  508. */
  509. if (active_events[hartid][cbase] != SBI_PMU_EVENT_IDX_INVALID)
  510. continue;
  511. /* If mcountinhibit is supported, the bit must be enabled */
  512. if ((sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11) &&
  513. !__test_bit(cbase, &mctr_inhbt))
  514. continue;
  515. /* We found a valid counter that is not started yet */
  516. ctr_idx = cbase;
  517. }
  518. }
  519. if (ctr_idx == SBI_ENOTSUPP) {
  520. /**
  521. * We can't find any programmable counters for cycle/instret.
  522. * Return the fixed counter as they are mandatory anyways.
  523. */
  524. if (fixed_ctr >= 0)
  525. return fixed_ctr;
  526. else
  527. return SBI_EFAIL;
  528. }
  529. ret = pmu_update_hw_mhpmevent(temp, ctr_idx, flags, event_idx, data);
  530. if (!ret)
  531. ret = ctr_idx;
  532. return ret;
  533. }
  534. /**
  535. * Any firmware counter can map to any firmware event.
  536. * Thus, select the first available fw counter after sanity
  537. * check.
  538. */
  539. static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask,
  540. uint32_t event_code, u32 hartid)
  541. {
  542. int i, cidx;
  543. for_each_set_bit(i, &cmask, BITS_PER_LONG) {
  544. cidx = i + cbase;
  545. if (cidx < num_hw_ctrs || total_ctrs <= cidx)
  546. continue;
  547. if (active_events[hartid][i] != SBI_PMU_EVENT_IDX_INVALID)
  548. continue;
  549. if (SBI_PMU_FW_MAX <= event_code &&
  550. pmu_dev && pmu_dev->fw_counter_match_code) {
  551. if (!pmu_dev->fw_counter_match_code(cidx - num_hw_ctrs,
  552. event_code))
  553. continue;
  554. }
  555. return i;
  556. }
  557. return SBI_ENOTSUPP;
  558. }
  559. int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
  560. unsigned long flags, unsigned long event_idx,
  561. uint64_t event_data)
  562. {
  563. int ret, ctr_idx = SBI_ENOTSUPP;
  564. u32 event_code, hartid = current_hartid();
  565. int event_type;
  566. /* Do a basic sanity check of counter base & mask */
  567. if ((cidx_base + sbi_fls(cidx_mask)) >= total_ctrs)
  568. return SBI_EINVAL;
  569. event_type = pmu_event_validate(event_idx);
  570. if (event_type < 0)
  571. return SBI_EINVAL;
  572. event_code = get_cidx_code(event_idx);
  573. if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) {
  574. /* The caller wants to skip the match because it already knows the
  575. * counter idx for the given event. Verify that the counter idx
  576. * is still valid.
  577. */
  578. if (active_events[hartid][cidx_base] == SBI_PMU_EVENT_IDX_INVALID)
  579. return SBI_EINVAL;
  580. ctr_idx = cidx_base;
  581. goto skip_match;
  582. }
  583. if (event_type == SBI_PMU_EVENT_TYPE_FW) {
  584. /* Any firmware counter can be used track any firmware event */
  585. ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code, hartid);
  586. } else {
  587. ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx,
  588. event_data);
  589. }
  590. if (ctr_idx < 0)
  591. return SBI_ENOTSUPP;
  592. active_events[hartid][ctr_idx] = event_idx;
  593. skip_match:
  594. if (event_type == SBI_PMU_EVENT_TYPE_HW) {
  595. if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE)
  596. pmu_ctr_write_hw(ctr_idx, 0);
  597. if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
  598. pmu_ctr_start_hw(ctr_idx, 0, false);
  599. } else if (event_type == SBI_PMU_EVENT_TYPE_FW) {
  600. if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE)
  601. fw_counters_value[hartid][ctr_idx - num_hw_ctrs] = 0;
  602. if (flags & SBI_PMU_CFG_FLAG_AUTO_START) {
  603. if (SBI_PMU_FW_MAX <= event_code &&
  604. pmu_dev && pmu_dev->fw_counter_start) {
  605. ret = pmu_dev->fw_counter_start(
  606. ctr_idx - num_hw_ctrs, event_code,
  607. fw_counters_value[hartid][ctr_idx - num_hw_ctrs],
  608. true);
  609. if (ret)
  610. return ret;
  611. }
  612. fw_counters_started[hartid] |= BIT(ctr_idx - num_hw_ctrs);
  613. }
  614. }
  615. return ctr_idx;
  616. }
  617. int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id)
  618. {
  619. u32 cidx, hartid = current_hartid();
  620. uint64_t *fcounter = NULL;
  621. if (likely(!fw_counters_started[hartid]))
  622. return 0;
  623. if (unlikely(fw_id >= SBI_PMU_FW_MAX))
  624. return SBI_EINVAL;
  625. for (cidx = num_hw_ctrs; cidx < total_ctrs; cidx++) {
  626. if (get_cidx_code(active_events[hartid][cidx]) == fw_id &&
  627. (fw_counters_started[hartid] & BIT(cidx - num_hw_ctrs))) {
  628. fcounter = &fw_counters_value[hartid][cidx - num_hw_ctrs];
  629. break;
  630. }
  631. }
  632. if (fcounter)
  633. (*fcounter)++;
  634. return 0;
  635. }
  636. unsigned long sbi_pmu_num_ctr(void)
  637. {
  638. return (num_hw_ctrs + SBI_PMU_FW_CTR_MAX);
  639. }
  640. int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info)
  641. {
  642. union sbi_pmu_ctr_info cinfo = {0};
  643. struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
  644. /* Sanity check. Counter1 is not mapped at all */
  645. if (cidx >= total_ctrs || cidx == 1)
  646. return SBI_EINVAL;
  647. /* We have 31 HW counters with 31 being the last index(MHPMCOUNTER31) */
  648. if (cidx < num_hw_ctrs) {
  649. cinfo.type = SBI_PMU_CTR_TYPE_HW;
  650. cinfo.csr = CSR_CYCLE + cidx;
  651. /* mcycle & minstret are always 64 bit */
  652. if (cidx == 0 || cidx == 2)
  653. cinfo.width = 63;
  654. else
  655. cinfo.width = sbi_hart_mhpm_bits(scratch) - 1;
  656. } else {
  657. /* it's a firmware counter */
  658. cinfo.type = SBI_PMU_CTR_TYPE_FW;
  659. /* Firmware counters are always 64 bits wide */
  660. cinfo.width = 63;
  661. }
  662. *ctr_info = cinfo.value;
  663. return 0;
  664. }
  665. static void pmu_reset_event_map(u32 hartid)
  666. {
  667. int j;
  668. /* Initialize the counter to event mapping table */
  669. for (j = 3; j < total_ctrs; j++)
  670. active_events[hartid][j] = SBI_PMU_EVENT_IDX_INVALID;
  671. for (j = 0; j < SBI_PMU_FW_CTR_MAX; j++)
  672. fw_counters_value[hartid][j] = 0;
  673. fw_counters_started[hartid] = 0;
  674. }
  675. const struct sbi_pmu_device *sbi_pmu_get_device(void)
  676. {
  677. return pmu_dev;
  678. }
  679. void sbi_pmu_set_device(const struct sbi_pmu_device *dev)
  680. {
  681. if (!dev || pmu_dev)
  682. return;
  683. pmu_dev = dev;
  684. }
  685. void sbi_pmu_exit(struct sbi_scratch *scratch)
  686. {
  687. u32 hartid = current_hartid();
  688. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11)
  689. csr_write(CSR_MCOUNTINHIBIT, 0xFFFFFFF8);
  690. if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_10)
  691. csr_write(CSR_MCOUNTEREN, -1);
  692. pmu_reset_event_map(hartid);
  693. }
  694. int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
  695. {
  696. const struct sbi_platform *plat;
  697. u32 hartid = current_hartid();
  698. if (cold_boot) {
  699. plat = sbi_platform_ptr(scratch);
  700. /* Initialize hw pmu events */
  701. sbi_platform_pmu_init(plat);
  702. /* mcycle & minstret is available always */
  703. num_hw_ctrs = sbi_hart_mhpm_count(scratch) + 3;
  704. total_ctrs = num_hw_ctrs + SBI_PMU_FW_CTR_MAX;
  705. }
  706. pmu_reset_event_map(hartid);
  707. /* First three counters are fixed by the priv spec and we enable it by default */
  708. active_events[hartid][0] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET |
  709. SBI_PMU_HW_CPU_CYCLES;
  710. active_events[hartid][1] = SBI_PMU_EVENT_IDX_INVALID;
  711. active_events[hartid][2] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET |
  712. SBI_PMU_HW_INSTRUCTIONS;
  713. return 0;
  714. }