sbi_hart.c 7.5 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_barrier.h>
  11. #include <sbi/riscv_encoding.h>
  12. #include <sbi/riscv_fp.h>
  13. #include <sbi/riscv_locks.h>
  14. #include <sbi/sbi_bits.h>
  15. #include <sbi/sbi_console.h>
  16. #include <sbi/sbi_error.h>
  17. #include <sbi/sbi_hart.h>
  18. #include <sbi/sbi_platform.h>
  19. /**
  20. * Return HART ID of the caller.
  21. */
  22. unsigned int sbi_current_hartid()
  23. {
  24. return (u32)csr_read(CSR_MHARTID);
  25. }
  26. static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
  27. {
  28. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  29. /* Enable FPU */
  30. if (misa_extension('D') || misa_extension('F'))
  31. csr_write(CSR_MSTATUS, MSTATUS_FS);
  32. /* Enable user/supervisor use of perf counters */
  33. if (misa_extension('S') &&
  34. sbi_platform_has_scounteren(plat))
  35. csr_write(CSR_SCOUNTEREN, -1);
  36. if (sbi_platform_has_mcounteren(plat))
  37. csr_write(CSR_MCOUNTEREN, -1);
  38. /* Disable all interrupts */
  39. csr_write(CSR_MIE, 0);
  40. /* Disable S-mode paging */
  41. if (misa_extension('S'))
  42. csr_write(CSR_SATP, 0);
  43. }
  44. static int fp_init(u32 hartid)
  45. {
  46. #ifdef __riscv_flen
  47. int i;
  48. #else
  49. unsigned long fd_mask;
  50. #endif
  51. if (!misa_extension('D') && !misa_extension('F'))
  52. return 0;
  53. if (!(csr_read(CSR_MSTATUS) & MSTATUS_FS))
  54. return SBI_EINVAL;
  55. #ifdef __riscv_flen
  56. for (i = 0; i < 32; i++)
  57. init_fp_reg(i);
  58. csr_write(CSR_FCSR, 0);
  59. #else
  60. fd_mask = (1 << ('F' - 'A')) | (1 << ('D' - 'A'));
  61. csr_clear(CSR_MISA, fd_mask);
  62. if (csr_read(CSR_MISA) & fd_mask)
  63. return SBI_ENOTSUPP;
  64. #endif
  65. return 0;
  66. }
  67. static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
  68. {
  69. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  70. unsigned long interrupts, exceptions;
  71. if (!misa_extension('S'))
  72. /* No delegation possible as mideleg does not exist*/
  73. return 0;
  74. /* Send M-mode interrupts and most exceptions to S-mode */
  75. interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
  76. exceptions = (1U << CAUSE_MISALIGNED_FETCH) |
  77. (1U << CAUSE_BREAKPOINT) |
  78. (1U << CAUSE_USER_ECALL);
  79. if (sbi_platform_has_mfaults_delegation(plat))
  80. exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) |
  81. (1U << CAUSE_LOAD_PAGE_FAULT) |
  82. (1U << CAUSE_STORE_PAGE_FAULT);
  83. csr_write(CSR_MIDELEG, interrupts);
  84. csr_write(CSR_MEDELEG, exceptions);
  85. if (csr_read(CSR_MIDELEG) != interrupts)
  86. return SBI_EFAIL;
  87. if (csr_read(CSR_MEDELEG) != exceptions)
  88. return SBI_EFAIL;
  89. return 0;
  90. }
  91. unsigned long log2roundup(unsigned long x)
  92. {
  93. unsigned long ret = 0;
  94. while (ret < __riscv_xlen) {
  95. if (x <= (1UL << ret))
  96. break;
  97. ret++;
  98. }
  99. return ret;
  100. }
  101. void sbi_hart_pmp_dump(struct sbi_scratch *scratch)
  102. {
  103. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  104. unsigned long prot, addr, size, l2l;
  105. unsigned int i;
  106. if (!sbi_platform_has_pmp(plat))
  107. return;
  108. for (i = 0; i < PMP_COUNT; i++) {
  109. pmp_get(i, &prot, &addr, &l2l);
  110. if (!(prot & PMP_A))
  111. continue;
  112. if (l2l < __riscv_xlen)
  113. size = (1UL << l2l);
  114. else
  115. size = 0;
  116. #if __riscv_xlen == 32
  117. sbi_printf("PMP%d: 0x%08lx-0x%08lx (A",
  118. #else
  119. sbi_printf("PMP%d: 0x%016lx-0x%016lx (A",
  120. #endif
  121. i, addr, addr + size - 1);
  122. if (prot & PMP_L)
  123. sbi_printf(",L");
  124. if (prot & PMP_R)
  125. sbi_printf(",R");
  126. if (prot & PMP_W)
  127. sbi_printf(",W");
  128. if (prot & PMP_X)
  129. sbi_printf(",X");
  130. sbi_printf(")\n");
  131. }
  132. }
  133. static int pmp_init(struct sbi_scratch *scratch, u32 hartid)
  134. {
  135. u32 i, count;
  136. unsigned long fw_start, fw_size_log2;
  137. ulong prot, addr, log2size;
  138. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  139. if (!sbi_platform_has_pmp(plat))
  140. return 0;
  141. fw_size_log2 = log2roundup(scratch->fw_size);
  142. fw_start = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
  143. pmp_set(0, 0, fw_start, fw_size_log2);
  144. count = sbi_platform_pmp_region_count(plat, hartid);
  145. if ((PMP_COUNT - 1) < count)
  146. count = (PMP_COUNT - 1);
  147. for (i = 0; i < count; i++) {
  148. if (sbi_platform_pmp_region_info(plat, hartid, i,
  149. &prot, &addr, &log2size))
  150. continue;
  151. pmp_set(i + 1, prot, addr, log2size);
  152. }
  153. return 0;
  154. }
  155. int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid)
  156. {
  157. int rc;
  158. mstatus_init(scratch, hartid);
  159. rc = fp_init(hartid);
  160. if (rc)
  161. return rc;
  162. rc = delegate_traps(scratch, hartid);
  163. if (rc)
  164. return rc;
  165. return pmp_init(scratch, hartid);
  166. }
  167. void __attribute__((noreturn)) sbi_hart_hang(void)
  168. {
  169. while (1)
  170. wfi();
  171. __builtin_unreachable();
  172. }
  173. void __attribute__((noreturn)) sbi_hart_switch_mode(unsigned long arg0,
  174. unsigned long arg1,
  175. unsigned long next_addr,
  176. unsigned long next_mode)
  177. {
  178. unsigned long val;
  179. switch (next_mode) {
  180. case PRV_M:
  181. break;
  182. case PRV_S:
  183. if (!misa_extension('S'))
  184. sbi_hart_hang();
  185. break;
  186. case PRV_U:
  187. if (!misa_extension('U'))
  188. sbi_hart_hang();
  189. break;
  190. default:
  191. sbi_hart_hang();
  192. }
  193. val = csr_read(CSR_MSTATUS);
  194. val = INSERT_FIELD(val, MSTATUS_MPP, next_mode);
  195. val = INSERT_FIELD(val, MSTATUS_MPIE, 0);
  196. csr_write(CSR_MSTATUS, val);
  197. csr_write(CSR_MEPC, next_addr);
  198. if (next_mode == PRV_S) {
  199. csr_write(CSR_STVEC, next_addr);
  200. csr_write(CSR_SSCRATCH, 0);
  201. csr_write(CSR_SIE, 0);
  202. csr_write(CSR_SATP, 0);
  203. } else if (next_mode == PRV_U) {
  204. csr_write(CSR_UTVEC, next_addr);
  205. csr_write(CSR_USCRATCH, 0);
  206. csr_write(CSR_UIE, 0);
  207. }
  208. register unsigned long a0 asm ("a0") = arg0;
  209. register unsigned long a1 asm ("a1") = arg1;
  210. __asm__ __volatile__ ("mret" : : "r" (a0), "r" (a1));
  211. __builtin_unreachable();
  212. }
  213. static spinlock_t avail_hart_mask_lock = SPIN_LOCK_INITIALIZER;
  214. static volatile unsigned long avail_hart_mask = 0;
  215. void sbi_hart_mark_available(u32 hartid)
  216. {
  217. spin_lock(&avail_hart_mask_lock);
  218. avail_hart_mask |= (1UL << hartid);
  219. spin_unlock(&avail_hart_mask_lock);
  220. }
  221. void sbi_hart_unmark_available(u32 hartid)
  222. {
  223. spin_lock(&avail_hart_mask_lock);
  224. avail_hart_mask &= ~(1UL << hartid);
  225. spin_unlock(&avail_hart_mask_lock);
  226. }
  227. ulong sbi_hart_available_mask(void)
  228. {
  229. ulong ret;
  230. spin_lock(&avail_hart_mask_lock);
  231. ret = avail_hart_mask;
  232. spin_unlock(&avail_hart_mask_lock);
  233. return ret;
  234. }
  235. typedef struct sbi_scratch *(*h2s)(ulong hartid);
  236. struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
  237. u32 hartid)
  238. {
  239. return ((h2s)scratch->hartid_to_scratch)(hartid);
  240. }
  241. #define COLDBOOT_WAIT_BITMAP_SIZE __riscv_xlen
  242. static spinlock_t coldboot_wait_bitmap_lock = SPIN_LOCK_INITIALIZER;
  243. static unsigned long coldboot_wait_bitmap = 0;
  244. void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
  245. {
  246. unsigned long mipval;
  247. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  248. if ((sbi_platform_hart_count(plat) <= hartid) ||
  249. (COLDBOOT_WAIT_BITMAP_SIZE <= hartid))
  250. sbi_hart_hang();
  251. /* Set MSIE bit to receive IPI */
  252. csr_set(CSR_MIE, MIP_MSIP);
  253. do {
  254. spin_lock(&coldboot_wait_bitmap_lock);
  255. coldboot_wait_bitmap |= (1UL << hartid);
  256. spin_unlock(&coldboot_wait_bitmap_lock);
  257. wfi();
  258. mipval = csr_read(CSR_MIP);
  259. spin_lock(&coldboot_wait_bitmap_lock);
  260. coldboot_wait_bitmap &= ~(1UL << hartid);
  261. spin_unlock(&coldboot_wait_bitmap_lock);
  262. } while (!(mipval && MIP_MSIP));
  263. csr_clear(CSR_MIP, MIP_MSIP);
  264. }
  265. void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
  266. {
  267. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  268. int max_hart = sbi_platform_hart_count(plat);
  269. for(int i = 0; i < max_hart ; i++) {
  270. /* send an IPI to every other hart */
  271. spin_lock(&coldboot_wait_bitmap_lock);
  272. if ((i != hartid) && (coldboot_wait_bitmap & (1UL << i)))
  273. sbi_platform_ipi_send(plat, i);
  274. spin_unlock(&coldboot_wait_bitmap_lock);
  275. }
  276. }