uarths.h 4.7 KB

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  1. /*
  2. * SPDX-License-Identifier: Apache-2.0
  3. *
  4. * Copyright 2018 Canaan Inc.
  5. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  6. *
  7. * Licensed under the Apache License, Version 2.0 (the "License");
  8. * you may not use this file except in compliance with the License.
  9. * You may obtain a copy of the License at
  10. *
  11. * http://www.apache.org/licenses/LICENSE-2.0
  12. *
  13. * Unless required by applicable law or agreed to in writing, software
  14. * distributed under the License is distributed on an "AS IS" BASIS,
  15. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  16. * See the License for the specific language governing permissions and
  17. * limitations under the License.
  18. */
  19. /*
  20. * Universal Asynchronous Receiver/Transmitter (UART)
  21. * The UART peripheral supports the following features:
  22. *
  23. * - 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start
  24. * bit, 1 or 2 stop bits
  25. *
  26. * - 8-entry transmit and receive FIFO buffers with programmable
  27. * watermark interrupts
  28. *
  29. * - 16× Rx oversampling with 2/3 majority voting per bit
  30. *
  31. * The UART peripheral does not support hardware flow control or
  32. * other modem control signals, or synchronous serial data
  33. * tranfesrs.
  34. *
  35. * UART RAM Layout
  36. * | Address | Name | Description |
  37. * |-----------|----------|---------------------------------|
  38. * | 0x000 | txdata | Transmit data register |
  39. * | 0x004 | rxdata | Receive data register |
  40. * | 0x008 | txctrl | Transmit control register |
  41. * | 0x00C | rxctrl | Receive control register |
  42. * | 0x010 | ie | UART interrupt enable |
  43. * | 0x014 | ip | UART Interrupt pending |
  44. * | 0x018 | div | Baud rate divisor |
  45. */
  46. #ifndef _K210_UARTHS_H_
  47. #define _K210_UARTHS_H_
  48. #include <sbi/sbi_types.h>
  49. /* clang-format off */
  50. /* Base register address */
  51. #define UARTHS_BASE_ADDR (0x38000000U)
  52. /* Register address offsets */
  53. #define UARTHS_REG_TXFIFO 0x00
  54. #define UARTHS_REG_RXFIFO 0x04
  55. #define UARTHS_REG_TXCTRL 0x08
  56. #define UARTHS_REG_RXCTRL 0x0c
  57. #define UARTHS_REG_IE 0x10
  58. #define UARTHS_REG_IP 0x14
  59. #define UARTHS_REG_DIV 0x18
  60. /* TXCTRL register */
  61. #define UARTHS_TXEN 0x01
  62. #define UARTHS_TXWM(x) (((x) & 0xffff) << 16)
  63. /* RXCTRL register */
  64. #define UARTHS_RXEN 0x01
  65. #define UARTHS_RXWM(x) (((x) & 0xffff) << 16)
  66. /* IP register */
  67. #define UARTHS_IP_TXWM 0x01
  68. #define UARTHS_IP_RXWM 0x02
  69. /* clang-format on */
  70. struct uarths_txdata {
  71. /* Bits [7:0] is data */
  72. u32 data : 8;
  73. /* Bits [30:8] is 0 */
  74. u32 zero : 23;
  75. /* Bit 31 is full status */
  76. u32 full : 1;
  77. } __attribute__((packed, aligned(4)));
  78. struct uarths_rxdata {
  79. /* Bits [7:0] is data */
  80. u32 data : 8;
  81. /* Bits [30:8] is 0 */
  82. u32 zero : 23;
  83. /* Bit 31 is empty status */
  84. u32 empty : 1;
  85. } __attribute__((packed, aligned(4)));
  86. struct uarths_txctrl {
  87. /* Bit 0 is txen, controls whether the Tx channel is active. */
  88. u32 txen : 1;
  89. /* Bit 1 is nstop, 0 for one stop bit and 1 for two stop bits */
  90. u32 nstop : 1;
  91. /* Bits [15:2] is reserved */
  92. u32 resv0 : 14;
  93. /* Bits [18:16] is threshold of interrupt triggers */
  94. u32 txcnt : 3;
  95. /* Bits [31:19] is reserved */
  96. u32 resv1 : 13;
  97. } __attribute__((packed, aligned(4)));
  98. struct uarths_rxctrl {
  99. /* Bit 0 is txen, controls whether the Tx channel is active. */
  100. u32 rxen : 1;
  101. /* Bits [15:1] is reserved */
  102. u32 resv0 : 15;
  103. /* Bits [18:16] is threshold of interrupt triggers */
  104. u32 rxcnt : 3;
  105. /* Bits [31:19] is reserved */
  106. u32 resv1 : 13;
  107. } __attribute__((packed, aligned(4)));
  108. struct uarths_ip {
  109. /* Bit 0 is txwm, raised less than txcnt */
  110. u32 txwm : 1;
  111. /* Bit 1 is txwm, raised greater than rxcnt */
  112. u32 rxwm : 1;
  113. /* Bits [31:2] is 0 */
  114. u32 zero : 30;
  115. } __attribute__((packed, aligned(4)));
  116. struct uarths_ie {
  117. /* Bit 0 is txwm, raised less than txcnt */
  118. u32 txwm : 1;
  119. /* Bit 1 is txwm, raised greater than rxcnt */
  120. u32 rxwm : 1;
  121. /* Bits [31:2] is 0 */
  122. u32 zero : 30;
  123. } __attribute__((packed, aligned(4)));
  124. struct uarths_div {
  125. /* Bits [31:2] is baud rate divisor register */
  126. u32 div : 16;
  127. /* Bits [31:16] is 0 */
  128. u32 zero : 16;
  129. } __attribute__((packed, aligned(4)));
  130. struct uarths {
  131. /* Address offset 0x00 */
  132. struct uarths_txdata txdata;
  133. /* Address offset 0x04 */
  134. struct uarths_rxdata rxdata;
  135. /* Address offset 0x08 */
  136. struct uarths_txctrl txctrl;
  137. /* Address offset 0x0c */
  138. struct uarths_rxctrl rxctrl;
  139. /* Address offset 0x10 */
  140. struct uarths_ie ie;
  141. /* Address offset 0x14 */
  142. struct uarths_ip ip;
  143. /* Address offset 0x18 */
  144. struct uarths_div div;
  145. } __attribute__((packed, aligned(4)));
  146. enum uarths_stopbit { UARTHS_STOP_1, UARTHS_STOP_2 };
  147. void uarths_init(u32 baud_rate, enum uarths_stopbit stopbit);
  148. void uarths_putc(char c);
  149. int uarths_getc(void);
  150. #endif /* _K210_UARTHS_H_ */