sysctl.h 20 KB

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  1. /*
  2. * SPDX-License-Identifier: Apache-2.0
  3. *
  4. * Copyright 2018 Canaan Inc.
  5. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  6. *
  7. * Licensed under the Apache License, Version 2.0 (the "License");
  8. * you may not use this file except in compliance with the License.
  9. * You may obtain a copy of the License at
  10. *
  11. * http://www.apache.org/licenses/LICENSE-2.0
  12. *
  13. * Unless required by applicable law or agreed to in writing, software
  14. * distributed under the License is distributed on an "AS IS" BASIS,
  15. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  16. * See the License for the specific language governing permissions and
  17. * limitations under the License.
  18. */
  19. #ifndef _K210_SYSCTL_H_
  20. #define _K210_SYSCTL_H_
  21. #include <sbi/sbi_types.h>
  22. #include "platform.h"
  23. /**
  24. * System controller registers
  25. *
  26. * | Offset | Name | Description |
  27. * |-----------|----------------|-------------------------------------|
  28. * | 0x00 | git_id | Git short commit id |
  29. * | 0x04 | clk_freq | System clock base frequency |
  30. * | 0x08 | pll0 | PLL0 controller |
  31. * | 0x0c | pll1 | PLL1 controller |
  32. * | 0x10 | pll2 | PLL2 controller |
  33. * | 0x14 | resv5 | Reserved |
  34. * | 0x18 | pll_lock | PLL lock tester |
  35. * | 0x1c | rom_error | AXI ROM detector |
  36. * | 0x20 | clk_sel0 | Clock select controller0 |
  37. * | 0x24 | clk_sel1 | Clock select controller1 |
  38. * | 0x28 | clk_en_cent | Central clock enable |
  39. * | 0x2c | clk_en_peri | Peripheral clock enable |
  40. * | 0x30 | soft_reset | Soft reset ctrl |
  41. * | 0x34 | peri_reset | Peripheral reset controller |
  42. * | 0x38 | clk_th0 | Clock threshold controller 0 |
  43. * | 0x3c | clk_th1 | Clock threshold controller 1 |
  44. * | 0x40 | clk_th2 | Clock threshold controller 2 |
  45. * | 0x44 | clk_th3 | Clock threshold controller 3 |
  46. * | 0x48 | clk_th4 | Clock threshold controller 4 |
  47. * | 0x4c | clk_th5 | Clock threshold controller 5 |
  48. * | 0x50 | clk_th6 | Clock threshold controller 6 |
  49. * | 0x54 | misc | Miscellaneous controller |
  50. * | 0x58 | peri | Peripheral controller |
  51. * | 0x5c | spi_sleep | SPI sleep controller |
  52. * | 0x60 | reset_status | Reset source status |
  53. * | 0x64 | dma_sel0 | DMA handshake selector |
  54. * | 0x68 | dma_sel1 | DMA handshake selector |
  55. * | 0x6c | power_sel | IO Power Mode Select controller |
  56. * | 0x70 | resv28 | Reserved |
  57. * | 0x74 | resv29 | Reserved |
  58. * | 0x78 | resv30 | Reserved |
  59. * | 0x7c | resv31 | Reserved |
  60. */
  61. typedef enum _sysctl_pll_t {
  62. SYSCTL_PLL0,
  63. SYSCTL_PLL1,
  64. SYSCTL_PLL2,
  65. SYSCTL_PLL_MAX
  66. } sysctl_pll_t;
  67. typedef enum _sysctl_clock_source_t {
  68. SYSCTL_SOURCE_IN0,
  69. SYSCTL_SOURCE_PLL0,
  70. SYSCTL_SOURCE_PLL1,
  71. SYSCTL_SOURCE_PLL2,
  72. SYSCTL_SOURCE_ACLK,
  73. SYSCTL_SOURCE_MAX
  74. } sysctl_clock_source_t;
  75. typedef enum _sysctl_dma_channel_t {
  76. SYSCTL_DMA_CHANNEL_0,
  77. SYSCTL_DMA_CHANNEL_1,
  78. SYSCTL_DMA_CHANNEL_2,
  79. SYSCTL_DMA_CHANNEL_3,
  80. SYSCTL_DMA_CHANNEL_4,
  81. SYSCTL_DMA_CHANNEL_5,
  82. SYSCTL_DMA_CHANNEL_MAX
  83. } sysctl_dma_channel_t;
  84. typedef enum _sysctl_dma_select_t {
  85. SYSCTL_DMA_SELECT_SSI0_RX_REQ,
  86. SYSCTL_DMA_SELECT_SSI0_TX_REQ,
  87. SYSCTL_DMA_SELECT_SSI1_RX_REQ,
  88. SYSCTL_DMA_SELECT_SSI1_TX_REQ,
  89. SYSCTL_DMA_SELECT_SSI2_RX_REQ,
  90. SYSCTL_DMA_SELECT_SSI2_TX_REQ,
  91. SYSCTL_DMA_SELECT_SSI3_RX_REQ,
  92. SYSCTL_DMA_SELECT_SSI3_TX_REQ,
  93. SYSCTL_DMA_SELECT_I2C0_RX_REQ,
  94. SYSCTL_DMA_SELECT_I2C0_TX_REQ,
  95. SYSCTL_DMA_SELECT_I2C1_RX_REQ,
  96. SYSCTL_DMA_SELECT_I2C1_TX_REQ,
  97. SYSCTL_DMA_SELECT_I2C2_RX_REQ,
  98. SYSCTL_DMA_SELECT_I2C2_TX_REQ,
  99. SYSCTL_DMA_SELECT_UART1_RX_REQ,
  100. SYSCTL_DMA_SELECT_UART1_TX_REQ,
  101. SYSCTL_DMA_SELECT_UART2_RX_REQ,
  102. SYSCTL_DMA_SELECT_UART2_TX_REQ,
  103. SYSCTL_DMA_SELECT_UART3_RX_REQ,
  104. SYSCTL_DMA_SELECT_UART3_TX_REQ,
  105. SYSCTL_DMA_SELECT_AES_REQ,
  106. SYSCTL_DMA_SELECT_SHA_RX_REQ,
  107. SYSCTL_DMA_SELECT_AI_RX_REQ,
  108. SYSCTL_DMA_SELECT_FFT_RX_REQ,
  109. SYSCTL_DMA_SELECT_FFT_TX_REQ,
  110. SYSCTL_DMA_SELECT_I2S0_TX_REQ,
  111. SYSCTL_DMA_SELECT_I2S0_RX_REQ,
  112. SYSCTL_DMA_SELECT_I2S1_TX_REQ,
  113. SYSCTL_DMA_SELECT_I2S1_RX_REQ,
  114. SYSCTL_DMA_SELECT_I2S2_TX_REQ,
  115. SYSCTL_DMA_SELECT_I2S2_RX_REQ,
  116. SYSCTL_DMA_SELECT_I2S0_BF_DIR_REQ,
  117. SYSCTL_DMA_SELECT_I2S0_BF_VOICE_REQ,
  118. SYSCTL_DMA_SELECT_MAX
  119. } sysctl_dma_select_t;
  120. /**
  121. * System controller clock id
  122. */
  123. typedef enum _sysctl_clock_t {
  124. SYSCTL_CLOCK_PLL0,
  125. SYSCTL_CLOCK_PLL1,
  126. SYSCTL_CLOCK_PLL2,
  127. SYSCTL_CLOCK_CPU,
  128. SYSCTL_CLOCK_SRAM0,
  129. SYSCTL_CLOCK_SRAM1,
  130. SYSCTL_CLOCK_APB0,
  131. SYSCTL_CLOCK_APB1,
  132. SYSCTL_CLOCK_APB2,
  133. SYSCTL_CLOCK_ROM,
  134. SYSCTL_CLOCK_DMA,
  135. SYSCTL_CLOCK_AI,
  136. SYSCTL_CLOCK_DVP,
  137. SYSCTL_CLOCK_FFT,
  138. SYSCTL_CLOCK_GPIO,
  139. SYSCTL_CLOCK_SPI0,
  140. SYSCTL_CLOCK_SPI1,
  141. SYSCTL_CLOCK_SPI2,
  142. SYSCTL_CLOCK_SPI3,
  143. SYSCTL_CLOCK_I2S0,
  144. SYSCTL_CLOCK_I2S1,
  145. SYSCTL_CLOCK_I2S2,
  146. SYSCTL_CLOCK_I2C0,
  147. SYSCTL_CLOCK_I2C1,
  148. SYSCTL_CLOCK_I2C2,
  149. SYSCTL_CLOCK_UART1,
  150. SYSCTL_CLOCK_UART2,
  151. SYSCTL_CLOCK_UART3,
  152. SYSCTL_CLOCK_AES,
  153. SYSCTL_CLOCK_FPIOA,
  154. SYSCTL_CLOCK_TIMER0,
  155. SYSCTL_CLOCK_TIMER1,
  156. SYSCTL_CLOCK_TIMER2,
  157. SYSCTL_CLOCK_WDT0,
  158. SYSCTL_CLOCK_WDT1,
  159. SYSCTL_CLOCK_SHA,
  160. SYSCTL_CLOCK_OTP,
  161. SYSCTL_CLOCK_RTC,
  162. SYSCTL_CLOCK_ACLK = 40,
  163. SYSCTL_CLOCK_HCLK,
  164. SYSCTL_CLOCK_IN0,
  165. SYSCTL_CLOCK_MAX
  166. } sysctl_clock_t;
  167. /**
  168. * System controller clock select id
  169. */
  170. typedef enum _sysctl_clock_select_t {
  171. SYSCTL_CLOCK_SELECT_PLL0_BYPASS,
  172. SYSCTL_CLOCK_SELECT_PLL1_BYPASS,
  173. SYSCTL_CLOCK_SELECT_PLL2_BYPASS,
  174. SYSCTL_CLOCK_SELECT_PLL2,
  175. SYSCTL_CLOCK_SELECT_ACLK,
  176. SYSCTL_CLOCK_SELECT_SPI3,
  177. SYSCTL_CLOCK_SELECT_TIMER0,
  178. SYSCTL_CLOCK_SELECT_TIMER1,
  179. SYSCTL_CLOCK_SELECT_TIMER2,
  180. SYSCTL_CLOCK_SELECT_SPI3_SAMPLE,
  181. SYSCTL_CLOCK_SELECT_MAX = 11
  182. } sysctl_clock_select_t;
  183. /**
  184. * System controller clock threshold id
  185. */
  186. typedef enum _sysctl_threshold_t {
  187. SYSCTL_THRESHOLD_ACLK,
  188. SYSCTL_THRESHOLD_APB0,
  189. SYSCTL_THRESHOLD_APB1,
  190. SYSCTL_THRESHOLD_APB2,
  191. SYSCTL_THRESHOLD_SRAM0,
  192. SYSCTL_THRESHOLD_SRAM1,
  193. SYSCTL_THRESHOLD_AI,
  194. SYSCTL_THRESHOLD_DVP,
  195. SYSCTL_THRESHOLD_ROM,
  196. SYSCTL_THRESHOLD_SPI0,
  197. SYSCTL_THRESHOLD_SPI1,
  198. SYSCTL_THRESHOLD_SPI2,
  199. SYSCTL_THRESHOLD_SPI3,
  200. SYSCTL_THRESHOLD_TIMER0,
  201. SYSCTL_THRESHOLD_TIMER1,
  202. SYSCTL_THRESHOLD_TIMER2,
  203. SYSCTL_THRESHOLD_I2S0,
  204. SYSCTL_THRESHOLD_I2S1,
  205. SYSCTL_THRESHOLD_I2S2,
  206. SYSCTL_THRESHOLD_I2S0_M,
  207. SYSCTL_THRESHOLD_I2S1_M,
  208. SYSCTL_THRESHOLD_I2S2_M,
  209. SYSCTL_THRESHOLD_I2C0,
  210. SYSCTL_THRESHOLD_I2C1,
  211. SYSCTL_THRESHOLD_I2C2,
  212. SYSCTL_THRESHOLD_WDT0,
  213. SYSCTL_THRESHOLD_WDT1,
  214. SYSCTL_THRESHOLD_MAX = 28
  215. } sysctl_threshold_t;
  216. /**
  217. * System controller reset control id
  218. */
  219. typedef enum _sysctl_reset_t {
  220. SYSCTL_RESET_SOC,
  221. SYSCTL_RESET_ROM,
  222. SYSCTL_RESET_DMA,
  223. SYSCTL_RESET_AI,
  224. SYSCTL_RESET_DVP,
  225. SYSCTL_RESET_FFT,
  226. SYSCTL_RESET_GPIO,
  227. SYSCTL_RESET_SPI0,
  228. SYSCTL_RESET_SPI1,
  229. SYSCTL_RESET_SPI2,
  230. SYSCTL_RESET_SPI3,
  231. SYSCTL_RESET_I2S0,
  232. SYSCTL_RESET_I2S1,
  233. SYSCTL_RESET_I2S2,
  234. SYSCTL_RESET_I2C0,
  235. SYSCTL_RESET_I2C1,
  236. SYSCTL_RESET_I2C2,
  237. SYSCTL_RESET_UART1,
  238. SYSCTL_RESET_UART2,
  239. SYSCTL_RESET_UART3,
  240. SYSCTL_RESET_AES,
  241. SYSCTL_RESET_FPIOA,
  242. SYSCTL_RESET_TIMER0,
  243. SYSCTL_RESET_TIMER1,
  244. SYSCTL_RESET_TIMER2,
  245. SYSCTL_RESET_WDT0,
  246. SYSCTL_RESET_WDT1,
  247. SYSCTL_RESET_SHA,
  248. SYSCTL_RESET_RTC,
  249. SYSCTL_RESET_MAX = 31
  250. } sysctl_reset_t;
  251. typedef enum _sysctl_power_bank {
  252. SYSCTL_POWER_BANK0,
  253. SYSCTL_POWER_BANK1,
  254. SYSCTL_POWER_BANK2,
  255. SYSCTL_POWER_BANK3,
  256. SYSCTL_POWER_BANK4,
  257. SYSCTL_POWER_BANK5,
  258. SYSCTL_POWER_BANK6,
  259. SYSCTL_POWER_BANK7,
  260. SYSCTL_POWER_BANK_MAX,
  261. } sysctl_power_bank_t;
  262. /**
  263. * System controller reset control id
  264. */
  265. typedef enum _sysctl_io_power_mode {
  266. SYSCTL_POWER_V33,
  267. SYSCTL_POWER_V18
  268. } sysctl_io_power_mode_t;
  269. /**
  270. * Git short commit id
  271. * No. 0 Register (0x00)
  272. */
  273. typedef struct _sysctl_git_id {
  274. u32 git_id : 32;
  275. } __attribute__((packed, aligned(4))) sysctl_git_id_t;
  276. /**
  277. * System clock base frequency
  278. * No. 1 Register (0x04)
  279. */
  280. typedef struct _sysctl_clk_freq {
  281. u32 clk_freq : 32;
  282. } __attribute__((packed, aligned(4))) sysctl_clk_freq_t;
  283. /**
  284. * PLL0 controller
  285. * No. 2 Register (0x08)
  286. */
  287. typedef struct _sysctl_pll0 {
  288. u32 clkr0 : 4;
  289. u32 clkf0 : 6;
  290. u32 clkod0 : 4;
  291. u32 bwadj0 : 6;
  292. u32 pll_reset0 : 1;
  293. u32 pll_pwrd0 : 1;
  294. u32 pll_intfb0 : 1;
  295. u32 pll_bypass0 : 1;
  296. u32 pll_test0 : 1;
  297. u32 pll_out_en0 : 1;
  298. u32 pll_test_en : 1;
  299. u32 reserved : 5;
  300. } __attribute__((packed, aligned(4))) sysctl_pll0_t;
  301. /**
  302. * PLL1 controller
  303. * No. 3 Register (0x0c)
  304. */
  305. typedef struct _sysctl_pll1 {
  306. u32 clkr1 : 4;
  307. u32 clkf1 : 6;
  308. u32 clkod1 : 4;
  309. u32 bwadj1 : 6;
  310. u32 pll_reset1 : 1;
  311. u32 pll_pwrd1 : 1;
  312. u32 pll_intfb1 : 1;
  313. u32 pll_bypass1 : 1;
  314. u32 pll_test1 : 1;
  315. u32 pll_out_en1 : 1;
  316. u32 reserved : 6;
  317. } __attribute__((packed, aligned(4))) sysctl_pll1_t;
  318. /**
  319. * PLL2 controller
  320. * No. 4 Register (0x10)
  321. */
  322. typedef struct _sysctl_pll2 {
  323. u32 clkr2 : 4;
  324. u32 clkf2 : 6;
  325. u32 clkod2 : 4;
  326. u32 bwadj2 : 6;
  327. u32 pll_reset2 : 1;
  328. u32 pll_pwrd2 : 1;
  329. u32 pll_intfb2 : 1;
  330. u32 pll_bypass2 : 1;
  331. u32 pll_test2 : 1;
  332. u32 pll_out_en2 : 1;
  333. u32 pll_ckin_sel2 : 2;
  334. u32 reserved : 4;
  335. } __attribute__((packed, aligned(4))) sysctl_pll2_t;
  336. /**
  337. * PLL lock tester
  338. * No. 6 Register (0x18)
  339. */
  340. typedef struct _sysctl_pll_lock {
  341. u32 pll_lock0 : 2;
  342. u32 pll_slip_clear0 : 1;
  343. u32 test_clk_out0 : 1;
  344. u32 reserved0 : 4;
  345. u32 pll_lock1 : 2;
  346. u32 pll_slip_clear1 : 1;
  347. u32 test_clk_out1 : 1;
  348. u32 reserved1 : 4;
  349. u32 pll_lock2 : 2;
  350. u32 pll_slip_clear2 : 1;
  351. u32 test_clk_out2 : 1;
  352. u32 reserved2 : 12;
  353. } __attribute__((packed, aligned(4))) sysctl_pll_lock_t;
  354. /**
  355. * AXI ROM detector
  356. * No. 7 Register (0x1c)
  357. */
  358. typedef struct _sysctl_rom_error {
  359. u32 rom_mul_error : 1;
  360. u32 rom_one_error : 1;
  361. u32 reserved : 30;
  362. } __attribute__((packed, aligned(4))) sysctl_rom_error_t;
  363. /**
  364. * Clock select controller0
  365. * No. 8 Register (0x20)
  366. */
  367. typedef struct _sysctl_clk_sel0 {
  368. u32 aclk_sel : 1;
  369. u32 aclk_divider_sel : 2;
  370. u32 apb0_clk_sel : 3;
  371. u32 apb1_clk_sel : 3;
  372. u32 apb2_clk_sel : 3;
  373. u32 spi3_clk_sel : 1;
  374. u32 timer0_clk_sel : 1;
  375. u32 timer1_clk_sel : 1;
  376. u32 timer2_clk_sel : 1;
  377. u32 reserved : 16;
  378. } __attribute__((packed, aligned(4))) sysctl_clk_sel0_t;
  379. /**
  380. * Clock select controller1
  381. * No. 9 Register (0x24)
  382. */
  383. typedef struct _sysctl_clk_sel1 {
  384. u32 spi3_sample_clk_sel : 1;
  385. u32 reserved0 : 30;
  386. u32 reserved1 : 1;
  387. } __attribute__((packed, aligned(4))) sysctl_clk_sel1_t;
  388. /**
  389. * Central clock enable
  390. * No. 10 Register (0x28)
  391. */
  392. typedef struct _sysctl_clk_en_cent {
  393. u32 cpu_clk_en : 1;
  394. u32 sram0_clk_en : 1;
  395. u32 sram1_clk_en : 1;
  396. u32 apb0_clk_en : 1;
  397. u32 apb1_clk_en : 1;
  398. u32 apb2_clk_en : 1;
  399. u32 reserved : 26;
  400. } __attribute__((packed, aligned(4))) sysctl_clk_en_cent_t;
  401. /**
  402. * Peripheral clock enable
  403. * No. 11 Register (0x2c)
  404. */
  405. typedef struct _sysctl_clk_en_peri {
  406. u32 rom_clk_en : 1;
  407. u32 dma_clk_en : 1;
  408. u32 ai_clk_en : 1;
  409. u32 dvp_clk_en : 1;
  410. u32 fft_clk_en : 1;
  411. u32 gpio_clk_en : 1;
  412. u32 spi0_clk_en : 1;
  413. u32 spi1_clk_en : 1;
  414. u32 spi2_clk_en : 1;
  415. u32 spi3_clk_en : 1;
  416. u32 i2s0_clk_en : 1;
  417. u32 i2s1_clk_en : 1;
  418. u32 i2s2_clk_en : 1;
  419. u32 i2c0_clk_en : 1;
  420. u32 i2c1_clk_en : 1;
  421. u32 i2c2_clk_en : 1;
  422. u32 uart1_clk_en : 1;
  423. u32 uart2_clk_en : 1;
  424. u32 uart3_clk_en : 1;
  425. u32 aes_clk_en : 1;
  426. u32 fpioa_clk_en : 1;
  427. u32 timer0_clk_en : 1;
  428. u32 timer1_clk_en : 1;
  429. u32 timer2_clk_en : 1;
  430. u32 wdt0_clk_en : 1;
  431. u32 wdt1_clk_en : 1;
  432. u32 sha_clk_en : 1;
  433. u32 otp_clk_en : 1;
  434. u32 reserved : 1;
  435. u32 rtc_clk_en : 1;
  436. u32 reserved0 : 2;
  437. } __attribute__((packed, aligned(4))) sysctl_clk_en_peri_t;
  438. /**
  439. * Soft reset ctrl
  440. * No. 12 Register (0x30)
  441. */
  442. typedef struct _sysctl_soft_reset {
  443. u32 soft_reset : 1;
  444. u32 reserved : 31;
  445. } __attribute__((packed, aligned(4))) sysctl_soft_reset_t;
  446. /**
  447. * Peripheral reset controller
  448. * No. 13 Register (0x34)
  449. */
  450. typedef struct _sysctl_peri_reset {
  451. u32 rom_reset : 1;
  452. u32 dma_reset : 1;
  453. u32 ai_reset : 1;
  454. u32 dvp_reset : 1;
  455. u32 fft_reset : 1;
  456. u32 gpio_reset : 1;
  457. u32 spi0_reset : 1;
  458. u32 spi1_reset : 1;
  459. u32 spi2_reset : 1;
  460. u32 spi3_reset : 1;
  461. u32 i2s0_reset : 1;
  462. u32 i2s1_reset : 1;
  463. u32 i2s2_reset : 1;
  464. u32 i2c0_reset : 1;
  465. u32 i2c1_reset : 1;
  466. u32 i2c2_reset : 1;
  467. u32 uart1_reset : 1;
  468. u32 uart2_reset : 1;
  469. u32 uart3_reset : 1;
  470. u32 aes_reset : 1;
  471. u32 fpioa_reset : 1;
  472. u32 timer0_reset : 1;
  473. u32 timer1_reset : 1;
  474. u32 timer2_reset : 1;
  475. u32 wdt0_reset : 1;
  476. u32 wdt1_reset : 1;
  477. u32 sha_reset : 1;
  478. u32 reserved : 2;
  479. u32 rtc_reset : 1;
  480. u32 reserved0 : 2;
  481. } __attribute__((packed, aligned(4))) sysctl_peri_reset_t;
  482. /**
  483. * Clock threshold controller 0
  484. * No. 14 Register (0x38)
  485. */
  486. typedef struct _sysctl_clk_th0 {
  487. u32 sram0_gclk_threshold : 4;
  488. u32 sram1_gclk_threshold : 4;
  489. u32 ai_gclk_threshold : 4;
  490. u32 dvp_gclk_threshold : 4;
  491. u32 rom_gclk_threshold : 4;
  492. u32 reserved : 12;
  493. } __attribute__((packed, aligned(4))) sysctl_clk_th0_t;
  494. /**
  495. * Clock threshold controller 1
  496. * No. 15 Register (0x3c)
  497. */
  498. typedef struct _sysctl_clk_th1 {
  499. u32 spi0_clk_threshold : 8;
  500. u32 spi1_clk_threshold : 8;
  501. u32 spi2_clk_threshold : 8;
  502. u32 spi3_clk_threshold : 8;
  503. } __attribute__((packed, aligned(4))) sysctl_clk_th1_t;
  504. /**
  505. * Clock threshold controller 2
  506. * No. 16 Register (0x40)
  507. */
  508. typedef struct _sysctl_clk_th2 {
  509. u32 timer0_clk_threshold : 8;
  510. u32 timer1_clk_threshold : 8;
  511. u32 timer2_clk_threshold : 8;
  512. u32 reserved : 8;
  513. } __attribute__((packed, aligned(4))) sysctl_clk_th2_t;
  514. /**
  515. * Clock threshold controller 3
  516. * No. 17 Register (0x44)
  517. */
  518. typedef struct _sysctl_clk_th3 {
  519. u32 i2s0_clk_threshold : 16;
  520. u32 i2s1_clk_threshold : 16;
  521. } __attribute__((packed, aligned(4))) sysctl_clk_th3_t;
  522. /**
  523. * Clock threshold controller 4
  524. * No. 18 Register (0x48)
  525. */
  526. typedef struct _sysctl_clk_th4 {
  527. u32 i2s2_clk_threshold : 16;
  528. u32 i2s0_mclk_threshold : 8;
  529. u32 i2s1_mclk_threshold : 8;
  530. } __attribute__((packed, aligned(4))) sysctl_clk_th4_t;
  531. /**
  532. * Clock threshold controller 5
  533. * No. 19 Register (0x4c)
  534. */
  535. typedef struct _sysctl_clk_th5 {
  536. u32 i2s2_mclk_threshold : 8;
  537. u32 i2c0_clk_threshold : 8;
  538. u32 i2c1_clk_threshold : 8;
  539. u32 i2c2_clk_threshold : 8;
  540. } __attribute__((packed, aligned(4))) sysctl_clk_th5_t;
  541. /**
  542. * Clock threshold controller 6
  543. * No. 20 Register (0x50)
  544. */
  545. typedef struct _sysctl_clk_th6 {
  546. u32 wdt0_clk_threshold : 8;
  547. u32 wdt1_clk_threshold : 8;
  548. u32 reserved0 : 8;
  549. u32 reserved1 : 8;
  550. } __attribute__((packed, aligned(4))) sysctl_clk_th6_t;
  551. /**
  552. * Miscellaneous controller
  553. * No. 21 Register (0x54)
  554. */
  555. typedef struct _sysctl_misc {
  556. u32 debug_sel : 6;
  557. u32 reserved0 : 4;
  558. u32 spi_dvp_data_enable : 1;
  559. u32 reserved1 : 21;
  560. } __attribute__((packed, aligned(4))) sysctl_misc_t;
  561. /**
  562. * Peripheral controller
  563. * No. 22 Register (0x58)
  564. */
  565. typedef struct _sysctl_peri {
  566. u32 timer0_pause : 1;
  567. u32 timer1_pause : 1;
  568. u32 timer2_pause : 1;
  569. u32 timer3_pause : 1;
  570. u32 timer4_pause : 1;
  571. u32 timer5_pause : 1;
  572. u32 timer6_pause : 1;
  573. u32 timer7_pause : 1;
  574. u32 timer8_pause : 1;
  575. u32 timer9_pause : 1;
  576. u32 timer10_pause : 1;
  577. u32 timer11_pause : 1;
  578. u32 spi0_xip_en : 1;
  579. u32 spi1_xip_en : 1;
  580. u32 spi2_xip_en : 1;
  581. u32 spi3_xip_en : 1;
  582. u32 spi0_clk_bypass : 1;
  583. u32 spi1_clk_bypass : 1;
  584. u32 spi2_clk_bypass : 1;
  585. u32 i2s0_clk_bypass : 1;
  586. u32 i2s1_clk_bypass : 1;
  587. u32 i2s2_clk_bypass : 1;
  588. u32 jtag_clk_bypass : 1;
  589. u32 dvp_clk_bypass : 1;
  590. u32 debug_clk_bypass : 1;
  591. u32 reserved0 : 1;
  592. u32 reserved1 : 6;
  593. } __attribute__((packed, aligned(4))) sysctl_peri_t;
  594. /**
  595. * SPI sleep controller
  596. * No. 23 Register (0x5c)
  597. */
  598. typedef struct _sysctl_spi_sleep {
  599. u32 ssi0_sleep : 1;
  600. u32 ssi1_sleep : 1;
  601. u32 ssi2_sleep : 1;
  602. u32 ssi3_sleep : 1;
  603. u32 reserved : 28;
  604. } __attribute__((packed, aligned(4))) sysctl_spi_sleep_t;
  605. /**
  606. * Reset source status
  607. * No. 24 Register (0x60)
  608. */
  609. typedef struct _sysctl_reset_status {
  610. u32 reset_sts_clr : 1;
  611. u32 pin_reset_sts : 1;
  612. u32 wdt0_reset_sts : 1;
  613. u32 wdt1_reset_sts : 1;
  614. u32 soft_reset_sts : 1;
  615. u32 reserved : 27;
  616. } __attribute__((packed, aligned(4))) sysctl_reset_status_t;
  617. /**
  618. * DMA handshake selector
  619. * No. 25 Register (0x64)
  620. */
  621. typedef struct _sysctl_dma_sel0 {
  622. u32 dma_sel0 : 6;
  623. u32 dma_sel1 : 6;
  624. u32 dma_sel2 : 6;
  625. u32 dma_sel3 : 6;
  626. u32 dma_sel4 : 6;
  627. u32 reserved : 2;
  628. } __attribute__((packed, aligned(4))) sysctl_dma_sel0_t;
  629. /**
  630. * DMA handshake selector
  631. * No. 26 Register (0x68)
  632. */
  633. typedef struct _sysctl_dma_sel1 {
  634. u32 dma_sel5 : 6;
  635. u32 reserved : 26;
  636. } __attribute__((packed, aligned(4))) sysctl_dma_sel1_t;
  637. /**
  638. * IO Power Mode Select controller
  639. * No. 27 Register (0x6c)
  640. */
  641. typedef struct _sysctl_power_sel {
  642. u32 power_mode_sel0 : 1;
  643. u32 power_mode_sel1 : 1;
  644. u32 power_mode_sel2 : 1;
  645. u32 power_mode_sel3 : 1;
  646. u32 power_mode_sel4 : 1;
  647. u32 power_mode_sel5 : 1;
  648. u32 power_mode_sel6 : 1;
  649. u32 power_mode_sel7 : 1;
  650. u32 reserved : 24;
  651. } __attribute__((packed, aligned(4))) sysctl_power_sel_t;
  652. /**
  653. * System controller object
  654. *
  655. * The System controller is a peripheral device mapped in the
  656. * internal memory map, discoverable in the Configuration String.
  657. * It is responsible for low-level configuration of all system
  658. * related peripheral device. It contain PLL controller, clock
  659. * controller, reset controller, DMA handshake controller, SPI
  660. * controller, timer controller, WDT controller and sleep
  661. * controller.
  662. */
  663. typedef struct _sysctl {
  664. /* No. 0 (0x00): Git short commit id */
  665. sysctl_git_id_t git_id;
  666. /* No. 1 (0x04): System clock base frequency */
  667. sysctl_clk_freq_t clk_freq;
  668. /* No. 2 (0x08): PLL0 controller */
  669. sysctl_pll0_t pll0;
  670. /* No. 3 (0x0c): PLL1 controller */
  671. sysctl_pll1_t pll1;
  672. /* No. 4 (0x10): PLL2 controller */
  673. sysctl_pll2_t pll2;
  674. /* No. 5 (0x14): Reserved */
  675. u32 resv5;
  676. /* No. 6 (0x18): PLL lock tester */
  677. sysctl_pll_lock_t pll_lock;
  678. /* No. 7 (0x1c): AXI ROM detector */
  679. sysctl_rom_error_t rom_error;
  680. /* No. 8 (0x20): Clock select controller0 */
  681. sysctl_clk_sel0_t clk_sel0;
  682. /* No. 9 (0x24): Clock select controller1 */
  683. sysctl_clk_sel1_t clk_sel1;
  684. /* No. 10 (0x28): Central clock enable */
  685. sysctl_clk_en_cent_t clk_en_cent;
  686. /* No. 11 (0x2c): Peripheral clock enable */
  687. sysctl_clk_en_peri_t clk_en_peri;
  688. /* No. 12 (0x30): Soft reset ctrl */
  689. sysctl_soft_reset_t soft_reset;
  690. /* No. 13 (0x34): Peripheral reset controller */
  691. sysctl_peri_reset_t peri_reset;
  692. /* No. 14 (0x38): Clock threshold controller 0 */
  693. sysctl_clk_th0_t clk_th0;
  694. /* No. 15 (0x3c): Clock threshold controller 1 */
  695. sysctl_clk_th1_t clk_th1;
  696. /* No. 16 (0x40): Clock threshold controller 2 */
  697. sysctl_clk_th2_t clk_th2;
  698. /* No. 17 (0x44): Clock threshold controller 3 */
  699. sysctl_clk_th3_t clk_th3;
  700. /* No. 18 (0x48): Clock threshold controller 4 */
  701. sysctl_clk_th4_t clk_th4;
  702. /* No. 19 (0x4c): Clock threshold controller 5 */
  703. sysctl_clk_th5_t clk_th5;
  704. /* No. 20 (0x50): Clock threshold controller 6 */
  705. sysctl_clk_th6_t clk_th6;
  706. /* No. 21 (0x54): Miscellaneous controller */
  707. sysctl_misc_t misc;
  708. /* No. 22 (0x58): Peripheral controller */
  709. sysctl_peri_t peri;
  710. /* No. 23 (0x5c): SPI sleep controller */
  711. sysctl_spi_sleep_t spi_sleep;
  712. /* No. 24 (0x60): Reset source status */
  713. sysctl_reset_status_t reset_status;
  714. /* No. 25 (0x64): DMA handshake selector */
  715. sysctl_dma_sel0_t dma_sel0;
  716. /* No. 26 (0x68): DMA handshake selector */
  717. sysctl_dma_sel1_t dma_sel1;
  718. /* No. 27 (0x6c): IO Power Mode Select controller */
  719. sysctl_power_sel_t power_sel;
  720. /* No. 28 (0x70): Reserved */
  721. u32 resv28;
  722. /* No. 29 (0x74): Reserved */
  723. u32 resv29;
  724. /* No. 30 (0x78): Reserved */
  725. u32 resv30;
  726. /* No. 31 (0x7c): Reserved */
  727. u32 resv31;
  728. } __attribute__((packed, aligned(4))) sysctl_t;
  729. /**
  730. * Abstruct PLL struct
  731. */
  732. typedef struct _sysctl_general_pll {
  733. u32 clkr : 4;
  734. u32 clkf : 6;
  735. u32 clkod : 4;
  736. u32 bwadj : 6;
  737. u32 pll_reset : 1;
  738. u32 pll_pwrd : 1;
  739. u32 pll_intfb : 1;
  740. u32 pll_bypass : 1;
  741. u32 pll_test : 1;
  742. u32 pll_out_en : 1;
  743. u32 pll_ckin_sel : 2;
  744. u32 reserved : 4;
  745. } __attribute__((packed, aligned(4))) sysctl_general_pll_t;
  746. /**
  747. * Get frequency of CPU
  748. * @return The frequency of the CPU
  749. */
  750. u32 sysctl_get_cpu_freq(void);
  751. #endif /* _K210_SYSCTL_H_ */