plic.c 2.7 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_io.h>
  10. #include <sbi/riscv_encoding.h>
  11. #include <sbi/sbi_console.h>
  12. #include <plat/string.h>
  13. #include <plat/tinyfdt.h>
  14. #include <plat/irqchip/plic.h>
  15. #define PLIC_PRIORITY_BASE 0x0
  16. #define PLIC_PENDING_BASE 0x1000
  17. #define PLIC_ENABLE_BASE 0x2000
  18. #define PLIC_ENABLE_STRIDE 0x80
  19. #define PLIC_CONTEXT_BASE 0x200000
  20. #define PLIC_CONTEXT_STRIDE 0x1000
  21. static u32 plic_hart_count;
  22. static u32 plic_num_sources;
  23. static volatile void *plic_base;
  24. static void plic_set_priority(u32 source, u32 val)
  25. {
  26. volatile void *plic_priority =
  27. plic_base + PLIC_PRIORITY_BASE + 4 * source;
  28. writel(val, plic_priority);
  29. }
  30. static void plic_set_thresh(u32 cntxid, u32 val)
  31. {
  32. volatile void *plic_thresh =
  33. plic_base + PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
  34. writel(val, plic_thresh);
  35. }
  36. static void plic_set_ie(u32 cntxid, u32 word_index, u32 val)
  37. {
  38. volatile void *plic_ie =
  39. plic_base + PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid;
  40. writel(val, plic_ie + word_index * 4);
  41. }
  42. static void plic_fdt_fixup_prop(const struct fdt_node *node,
  43. const struct fdt_prop *prop, void *priv)
  44. {
  45. u32 *cells;
  46. u32 i, cells_count;
  47. if (!prop)
  48. return;
  49. if (strcmp(prop->name, "interrupts-extended"))
  50. return;
  51. cells = prop->value;
  52. cells_count = prop->len / sizeof(u32);
  53. if (!cells_count)
  54. return;
  55. for (i = 0; i < (cells_count / 2); i++) {
  56. if (fdt_rev32(cells[2 * i + 1]) == IRQ_M_EXT)
  57. cells[2 * i + 1] = fdt_rev32(0xffffffff);
  58. }
  59. }
  60. void plic_fdt_fixup(void *fdt, const char *compat)
  61. {
  62. fdt_compat_node_prop(fdt, compat, plic_fdt_fixup_prop, NULL);
  63. }
  64. int plic_warm_irqchip_init(u32 target_hart, int m_cntx_id, int s_cntx_id)
  65. {
  66. size_t i, ie_words = plic_num_sources / 32 + 1;
  67. if (plic_hart_count <= target_hart)
  68. return -1;
  69. /* By default, disable all IRQs for M-mode of target HART */
  70. if (m_cntx_id > -1) {
  71. for (i = 0; i < ie_words; i++)
  72. plic_set_ie(m_cntx_id, i, 0);
  73. }
  74. /* By default, disable all IRQs for S-mode of target HART */
  75. if (s_cntx_id > -1) {
  76. for (i = 0; i < ie_words; i++)
  77. plic_set_ie(s_cntx_id, i, 0);
  78. }
  79. /* By default, enable M-mode threshold */
  80. if (m_cntx_id > -1)
  81. plic_set_thresh(m_cntx_id, 1);
  82. /* By default, disable S-mode threshold */
  83. if (s_cntx_id > -1)
  84. plic_set_thresh(s_cntx_id, 0);
  85. return 0;
  86. }
  87. int plic_cold_irqchip_init(unsigned long base, u32 num_sources, u32 hart_count)
  88. {
  89. int i;
  90. plic_hart_count = hart_count;
  91. plic_num_sources = num_sources;
  92. plic_base = (void *)base;
  93. /* Configure default priorities of all IRQs */
  94. for (i = 1; i <= plic_num_sources; i++)
  95. plic_set_priority(i, 1);
  96. return 0;
  97. }