sbi_hart.c 7.5 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_barrier.h>
  11. #include <sbi/riscv_encoding.h>
  12. #include <sbi/riscv_fp.h>
  13. #include <sbi/riscv_locks.h>
  14. #include <sbi/sbi_bits.h>
  15. #include <sbi/sbi_console.h>
  16. #include <sbi/sbi_error.h>
  17. #include <sbi/sbi_hart.h>
  18. #include <sbi/sbi_platform.h>
  19. /**
  20. * Return HART ID of the caller.
  21. */
  22. unsigned int sbi_current_hartid()
  23. {
  24. return (u32)csr_read(CSR_MHARTID);
  25. }
  26. static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
  27. {
  28. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  29. /* Enable FPU */
  30. if (misa_extension('D') || misa_extension('F'))
  31. csr_write(CSR_MSTATUS, MSTATUS_FS);
  32. /* Enable user/supervisor use of perf counters */
  33. if (misa_extension('S') && sbi_platform_has_scounteren(plat))
  34. csr_write(CSR_SCOUNTEREN, -1);
  35. if (sbi_platform_has_mcounteren(plat))
  36. csr_write(CSR_MCOUNTEREN, -1);
  37. /* Disable all interrupts */
  38. csr_write(CSR_MIE, 0);
  39. /* Disable S-mode paging */
  40. if (misa_extension('S'))
  41. csr_write(CSR_SATP, 0);
  42. }
  43. static int fp_init(u32 hartid)
  44. {
  45. #ifdef __riscv_flen
  46. int i;
  47. #else
  48. unsigned long fd_mask;
  49. #endif
  50. if (!misa_extension('D') && !misa_extension('F'))
  51. return 0;
  52. if (!(csr_read(CSR_MSTATUS) & MSTATUS_FS))
  53. return SBI_EINVAL;
  54. #ifdef __riscv_flen
  55. for (i = 0; i < 32; i++)
  56. init_fp_reg(i);
  57. csr_write(CSR_FCSR, 0);
  58. #else
  59. fd_mask = (1 << ('F' - 'A')) | (1 << ('D' - 'A'));
  60. csr_clear(CSR_MISA, fd_mask);
  61. if (csr_read(CSR_MISA) & fd_mask)
  62. return SBI_ENOTSUPP;
  63. #endif
  64. return 0;
  65. }
  66. static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
  67. {
  68. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  69. unsigned long interrupts, exceptions;
  70. if (!misa_extension('S'))
  71. /* No delegation possible as mideleg does not exist*/
  72. return 0;
  73. /* Send M-mode interrupts and most exceptions to S-mode */
  74. interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
  75. exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_BREAKPOINT) |
  76. (1U << CAUSE_USER_ECALL);
  77. if (sbi_platform_has_mfaults_delegation(plat))
  78. exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) |
  79. (1U << CAUSE_LOAD_PAGE_FAULT) |
  80. (1U << CAUSE_STORE_PAGE_FAULT);
  81. csr_write(CSR_MIDELEG, interrupts);
  82. csr_write(CSR_MEDELEG, exceptions);
  83. if (csr_read(CSR_MIDELEG) != interrupts)
  84. return SBI_EFAIL;
  85. if (csr_read(CSR_MEDELEG) != exceptions)
  86. return SBI_EFAIL;
  87. return 0;
  88. }
  89. unsigned long log2roundup(unsigned long x)
  90. {
  91. unsigned long ret = 0;
  92. while (ret < __riscv_xlen) {
  93. if (x <= (1UL << ret))
  94. break;
  95. ret++;
  96. }
  97. return ret;
  98. }
  99. void sbi_hart_pmp_dump(struct sbi_scratch *scratch)
  100. {
  101. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  102. unsigned long prot, addr, size, l2l;
  103. unsigned int i;
  104. if (!sbi_platform_has_pmp(plat))
  105. return;
  106. for (i = 0; i < PMP_COUNT; i++) {
  107. pmp_get(i, &prot, &addr, &l2l);
  108. if (!(prot & PMP_A))
  109. continue;
  110. if (l2l < __riscv_xlen)
  111. size = (1UL << l2l);
  112. else
  113. size = 0;
  114. #if __riscv_xlen == 32
  115. sbi_printf("PMP%d: 0x%08lx-0x%08lx (A",
  116. #else
  117. sbi_printf("PMP%d: 0x%016lx-0x%016lx (A",
  118. #endif
  119. i, addr, addr + size - 1);
  120. if (prot & PMP_L)
  121. sbi_printf(",L");
  122. if (prot & PMP_R)
  123. sbi_printf(",R");
  124. if (prot & PMP_W)
  125. sbi_printf(",W");
  126. if (prot & PMP_X)
  127. sbi_printf(",X");
  128. sbi_printf(")\n");
  129. }
  130. }
  131. static int pmp_init(struct sbi_scratch *scratch, u32 hartid)
  132. {
  133. u32 i, count;
  134. unsigned long fw_start, fw_size_log2;
  135. ulong prot, addr, log2size;
  136. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  137. if (!sbi_platform_has_pmp(plat))
  138. return 0;
  139. fw_size_log2 = log2roundup(scratch->fw_size);
  140. fw_start = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
  141. pmp_set(0, 0, fw_start, fw_size_log2);
  142. count = sbi_platform_pmp_region_count(plat, hartid);
  143. if ((PMP_COUNT - 1) < count)
  144. count = (PMP_COUNT - 1);
  145. for (i = 0; i < count; i++) {
  146. if (sbi_platform_pmp_region_info(plat, hartid, i, &prot, &addr,
  147. &log2size))
  148. continue;
  149. pmp_set(i + 1, prot, addr, log2size);
  150. }
  151. return 0;
  152. }
  153. int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid)
  154. {
  155. int rc;
  156. mstatus_init(scratch, hartid);
  157. rc = fp_init(hartid);
  158. if (rc)
  159. return rc;
  160. rc = delegate_traps(scratch, hartid);
  161. if (rc)
  162. return rc;
  163. return pmp_init(scratch, hartid);
  164. }
  165. void __attribute__((noreturn)) sbi_hart_hang(void)
  166. {
  167. while (1)
  168. wfi();
  169. __builtin_unreachable();
  170. }
  171. void __attribute__((noreturn))
  172. sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
  173. unsigned long next_addr, unsigned long next_mode)
  174. {
  175. unsigned long val;
  176. switch (next_mode) {
  177. case PRV_M:
  178. break;
  179. case PRV_S:
  180. if (!misa_extension('S'))
  181. sbi_hart_hang();
  182. break;
  183. case PRV_U:
  184. if (!misa_extension('U'))
  185. sbi_hart_hang();
  186. break;
  187. default:
  188. sbi_hart_hang();
  189. }
  190. val = csr_read(CSR_MSTATUS);
  191. val = INSERT_FIELD(val, MSTATUS_MPP, next_mode);
  192. val = INSERT_FIELD(val, MSTATUS_MPIE, 0);
  193. csr_write(CSR_MSTATUS, val);
  194. csr_write(CSR_MEPC, next_addr);
  195. if (next_mode == PRV_S) {
  196. csr_write(CSR_STVEC, next_addr);
  197. csr_write(CSR_SSCRATCH, 0);
  198. csr_write(CSR_SIE, 0);
  199. csr_write(CSR_SATP, 0);
  200. } else if (next_mode == PRV_U) {
  201. csr_write(CSR_UTVEC, next_addr);
  202. csr_write(CSR_USCRATCH, 0);
  203. csr_write(CSR_UIE, 0);
  204. }
  205. register unsigned long a0 asm("a0") = arg0;
  206. register unsigned long a1 asm("a1") = arg1;
  207. __asm__ __volatile__("mret" : : "r"(a0), "r"(a1));
  208. __builtin_unreachable();
  209. }
  210. static spinlock_t avail_hart_mask_lock = SPIN_LOCK_INITIALIZER;
  211. static volatile unsigned long avail_hart_mask = 0;
  212. void sbi_hart_mark_available(u32 hartid)
  213. {
  214. spin_lock(&avail_hart_mask_lock);
  215. avail_hart_mask |= (1UL << hartid);
  216. spin_unlock(&avail_hart_mask_lock);
  217. }
  218. void sbi_hart_unmark_available(u32 hartid)
  219. {
  220. spin_lock(&avail_hart_mask_lock);
  221. avail_hart_mask &= ~(1UL << hartid);
  222. spin_unlock(&avail_hart_mask_lock);
  223. }
  224. ulong sbi_hart_available_mask(void)
  225. {
  226. ulong ret;
  227. spin_lock(&avail_hart_mask_lock);
  228. ret = avail_hart_mask;
  229. spin_unlock(&avail_hart_mask_lock);
  230. return ret;
  231. }
  232. typedef struct sbi_scratch *(*h2s)(ulong hartid);
  233. struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
  234. u32 hartid)
  235. {
  236. return ((h2s)scratch->hartid_to_scratch)(hartid);
  237. }
  238. #define COLDBOOT_WAIT_BITMAP_SIZE __riscv_xlen
  239. static spinlock_t coldboot_wait_bitmap_lock = SPIN_LOCK_INITIALIZER;
  240. static unsigned long coldboot_wait_bitmap = 0;
  241. void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
  242. {
  243. unsigned long mipval;
  244. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  245. if ((sbi_platform_hart_count(plat) <= hartid) ||
  246. (COLDBOOT_WAIT_BITMAP_SIZE <= hartid))
  247. sbi_hart_hang();
  248. /* Set MSIE bit to receive IPI */
  249. csr_set(CSR_MIE, MIP_MSIP);
  250. do {
  251. spin_lock(&coldboot_wait_bitmap_lock);
  252. coldboot_wait_bitmap |= (1UL << hartid);
  253. spin_unlock(&coldboot_wait_bitmap_lock);
  254. wfi();
  255. mipval = csr_read(CSR_MIP);
  256. spin_lock(&coldboot_wait_bitmap_lock);
  257. coldboot_wait_bitmap &= ~(1UL << hartid);
  258. spin_unlock(&coldboot_wait_bitmap_lock);
  259. } while (!(mipval && MIP_MSIP));
  260. csr_clear(CSR_MIP, MIP_MSIP);
  261. }
  262. void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
  263. {
  264. const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  265. int max_hart = sbi_platform_hart_count(plat);
  266. for (int i = 0; i < max_hart; i++) {
  267. /* send an IPI to every other hart */
  268. spin_lock(&coldboot_wait_bitmap_lock);
  269. if ((i != hartid) && (coldboot_wait_bitmap & (1UL << i)))
  270. sbi_platform_ipi_send(plat, i);
  271. spin_unlock(&coldboot_wait_bitmap_lock);
  272. }
  273. }