platform.c 5.2 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) Nuclei Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * lujun <lujun@nucleisys.com>
  8. * hqfang <578567190@qq.com>
  9. */
  10. #include <libfdt.h>
  11. #include <sbi/riscv_asm.h>
  12. #include <sbi/riscv_io.h>
  13. #include <sbi/riscv_encoding.h>
  14. #include <sbi/sbi_console.h>
  15. #include <sbi/sbi_const.h>
  16. #include <sbi/sbi_platform.h>
  17. #include <sbi_utils/fdt/fdt_fixup.h>
  18. #include <sbi_utils/irqchip/plic.h>
  19. #include <sbi_utils/serial/sifive-uart.h>
  20. #include <sbi_utils/sys/clint.h>
  21. /* clang-format off */
  22. #define UX600_HART_COUNT 1
  23. #define UX600_TIMER_FREQ 32768
  24. /* Nuclei timer base address */
  25. #define UX600_NUCLEI_TIMER_ADDR 0x2000000
  26. #define UX600_NUCLEI_TIMER_MSFTRST_OFS 0xFF0
  27. #define UX600_NUCLEI_TIMER_MSFTRST_KEY 0x80000A5F
  28. /* The clint compatiable timer offset is 0x1000 against nuclei timer */
  29. #define UX600_CLINT_TIMER_ADDR (UX600_NUCLEI_TIMER_ADDR + 0x1000)
  30. #define UX600_PLIC_ADDR 0x8000000
  31. #define UX600_PLIC_NUM_SOURCES 0x35
  32. #define UX600_PLIC_NUM_PRIORITIES 7
  33. #define UX600_UART0_ADDR 0x10013000
  34. #define UX600_UART1_ADDR 0x10023000
  35. #define UX600_DEBUG_UART UX600_UART0_ADDR
  36. #ifndef UX600_UART_BAUDRATE
  37. #define UX600_UART_BAUDRATE 57600
  38. #endif
  39. #define UX600_GPIO_ADDR 0x10012000
  40. #define UX600_GPIO_IOF_EN_OFS 0x38
  41. #define UX600_GPIO_IOF_SEL_OFS 0x3C
  42. #define UX600_GPIO_IOF_UART0_MASK 0x00030000
  43. #define UX600_TIMER_VALUE() readl((void *)UX600_NUCLEI_TIMER_ADDR)
  44. /* clang-format on */
  45. static u32 ux600_clk_freq = 8000000;
  46. static struct plic_data plic = {
  47. .addr = UX600_PLIC_ADDR,
  48. .num_src = UX600_PLIC_NUM_SOURCES,
  49. };
  50. static struct clint_data clint = {
  51. .addr = UX600_CLINT_TIMER_ADDR,
  52. .first_hartid = 0,
  53. .hart_count = UX600_HART_COUNT,
  54. .has_64bit_mmio = TRUE,
  55. };
  56. static u32 measure_cpu_freq(u32 n)
  57. {
  58. u32 start_mtime, delta_mtime;
  59. u32 mtime_freq = UX600_TIMER_FREQ;
  60. u32 tmp = (u32)UX600_TIMER_VALUE();
  61. u32 start_mcycle, delta_mcycle, freq;
  62. /* Don't start measuring until we see an mtime tick */
  63. do {
  64. start_mtime = (u32)UX600_TIMER_VALUE();
  65. } while (start_mtime == tmp);
  66. start_mcycle = csr_read(mcycle);
  67. do {
  68. delta_mtime = (u32)UX600_TIMER_VALUE() - start_mtime;
  69. } while (delta_mtime < n);
  70. delta_mcycle = csr_read(mcycle) - start_mcycle;
  71. freq = (delta_mcycle / delta_mtime) * mtime_freq
  72. + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
  73. return freq;
  74. }
  75. static u32 ux600_get_clk_freq(void)
  76. {
  77. u32 cpu_freq;
  78. /* warm up */
  79. measure_cpu_freq(1);
  80. /* measure for real */
  81. cpu_freq = measure_cpu_freq(100);
  82. return cpu_freq;
  83. }
  84. static int ux600_early_init(bool cold_boot)
  85. {
  86. u32 regval;
  87. /* Measure CPU Frequency using Timer */
  88. ux600_clk_freq = ux600_get_clk_freq();
  89. /* Init GPIO UART pinmux */
  90. regval = readl((void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_SEL_OFS)) &
  91. ~UX600_GPIO_IOF_UART0_MASK;
  92. writel(regval, (void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_SEL_OFS));
  93. regval = readl((void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_EN_OFS)) |
  94. UX600_GPIO_IOF_UART0_MASK;
  95. writel(regval, (void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_EN_OFS));
  96. return 0;
  97. }
  98. static void ux600_modify_dt(void *fdt)
  99. {
  100. fdt_fixups(fdt);
  101. }
  102. static int ux600_final_init(bool cold_boot)
  103. {
  104. void *fdt;
  105. if (!cold_boot)
  106. return 0;
  107. fdt = sbi_scratch_thishart_arg1_ptr();
  108. ux600_modify_dt(fdt);
  109. return 0;
  110. }
  111. static int ux600_console_init(void)
  112. {
  113. return sifive_uart_init(UX600_DEBUG_UART, ux600_clk_freq,
  114. UX600_UART_BAUDRATE);
  115. }
  116. static int ux600_irqchip_init(bool cold_boot)
  117. {
  118. int rc;
  119. u32 hartid = current_hartid();
  120. if (cold_boot) {
  121. rc = plic_cold_irqchip_init(&plic);
  122. if (rc)
  123. return rc;
  124. }
  125. return plic_warm_irqchip_init(&plic, (hartid) ? (2 * hartid - 1) : 0,
  126. (hartid) ? (2 * hartid) : -1);
  127. }
  128. static int ux600_ipi_init(bool cold_boot)
  129. {
  130. int rc;
  131. if (cold_boot) {
  132. rc = clint_cold_ipi_init(&clint);
  133. if (rc)
  134. return rc;
  135. }
  136. return clint_warm_ipi_init();
  137. }
  138. static int ux600_timer_init(bool cold_boot)
  139. {
  140. int rc;
  141. if (cold_boot) {
  142. rc = clint_cold_timer_init(&clint, NULL);
  143. if (rc)
  144. return rc;
  145. }
  146. return clint_warm_timer_init();
  147. }
  148. static int ux600_system_reset_check(u32 type, u32 reason)
  149. {
  150. return 1;
  151. }
  152. static void ux600_system_reset(u32 type, u32 reason)
  153. {
  154. /* Reset system using MSFTRST register in Nuclei Timer. */
  155. writel(UX600_NUCLEI_TIMER_MSFTRST_KEY, (void *)(UX600_NUCLEI_TIMER_ADDR
  156. + UX600_NUCLEI_TIMER_MSFTRST_OFS));
  157. while(1);
  158. }
  159. const struct sbi_platform_operations platform_ops = {
  160. .early_init = ux600_early_init,
  161. .final_init = ux600_final_init,
  162. .console_init = ux600_console_init,
  163. .irqchip_init = ux600_irqchip_init,
  164. .ipi_send = clint_ipi_send,
  165. .ipi_clear = clint_ipi_clear,
  166. .ipi_init = ux600_ipi_init,
  167. .timer_value = clint_timer_value,
  168. .timer_event_stop = clint_timer_event_stop,
  169. .timer_event_start = clint_timer_event_start,
  170. .timer_init = ux600_timer_init,
  171. .system_reset_check = ux600_system_reset_check,
  172. .system_reset = ux600_system_reset
  173. };
  174. const struct sbi_platform platform = {
  175. .opensbi_version = OPENSBI_VERSION,
  176. .platform_version = SBI_PLATFORM_VERSION(0x0U, 0x01U),
  177. .name = "Nuclei UX600",
  178. .features = SBI_PLATFORM_DEFAULT_FEATURES,
  179. .hart_count = UX600_HART_COUNT,
  180. .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
  181. .platform_ops_addr = (unsigned long)&platform_ops
  182. };