sbi_pmu.h 2.3 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #ifndef __SBI_PMU_H__
  10. #define __SBI_PMU_H__
  11. #include <sbi/sbi_types.h>
  12. #include <sbi/sbi_hartmask.h>
  13. #include <sbi/sbi_scratch.h>
  14. #include <sbi/sbi_ecall_interface.h>
  15. /* Event related macros */
  16. /* Maximum number of hardware events that can mapped by OpenSBI */
  17. #define SBI_PMU_HW_EVENT_MAX 256
  18. /* Maximum number of firmware events that can mapped by OpenSBI */
  19. #define SBI_PMU_FW_EVENT_MAX 32
  20. /* Counter related macros */
  21. #define SBI_PMU_FW_CTR_MAX 16
  22. #define SBI_PMU_HW_CTR_MAX 32
  23. #define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX)
  24. #define SBI_PMU_FIXED_CTR_MASK 0x07
  25. /** Initialize PMU */
  26. int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
  27. /** Reset PMU during hart exit */
  28. void sbi_pmu_exit(struct sbi_scratch *scratch);
  29. /**
  30. * Add the hardware event to counter mapping information. This should be called
  31. * from the platform code to update the mapping table.
  32. * @param eidx_start Start of the event idx range for supported counters
  33. * @param eidx_end End of the event idx range for supported counters
  34. * @param cmap A bitmap representing counters supporting the event range
  35. * @return 0 on success, error otherwise.
  36. */
  37. int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap);
  38. /**
  39. * Add the raw hardware event selector and supported counter information. This
  40. * should be called from the platform code to update the mapping table.
  41. * @param info a pointer to the hardware event info
  42. * @return 0 on success, error otherwise.
  43. */
  44. int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap);
  45. int sbi_pmu_ctr_read(uint32_t cidx, unsigned long *cval);
  46. int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask,
  47. unsigned long flag);
  48. int sbi_pmu_ctr_start(unsigned long cidx_base, unsigned long cidx_mask,
  49. unsigned long flags, uint64_t ival);
  50. int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info);
  51. unsigned long sbi_pmu_num_ctr(void);
  52. int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
  53. unsigned long flags, unsigned long event_idx,
  54. uint64_t event_data);
  55. int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id);
  56. #endif