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@@ -0,0 +1,84 @@
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+/*
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+ * SPDX-License-Identifier: BSD-2-Clause
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+ *
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+ * Copyright (c) 2022 StarFive Technology Co., Ltd.
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+ *
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+ * Author: Chee Hong Ang <cheehong.ang@linux.starfivetech.com>
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+ *
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+ */
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+
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+#define DUBHE_L2_CACHELINE_SIZE 0x40
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+
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+ /*
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+ * __sbi_dubhe_L2_inv_range(start,len)
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+ *
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+ * Invalidate the L2 cache within the specified region
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+ *
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+ * start - physical start address of region
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+ * len - size of memory region
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+ */
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+
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+ .align 3
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+ .global __sbi_dubhe_L2_inv_range
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+__sbi_dubhe_L2_inv_range:
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+ beqz a1, 4f
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+ li t0, DUBHE_L2_CACHELINE_SIZE
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+ addi t1, t0, -1
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+ add a1, a1, a0 /* Compute end address */
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+ and t2, a0, t1
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+ not t3, t1
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+ and a0, a0, t3
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+ beqz t2, 1f
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+ /* CFLUSH.L2 rs1 = a0 */
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+ fence rw, rw
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+ .insn i 0x73, 0, x0, a0, -0x3C
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+ fence rw, rw
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+ add a0, a0, t0
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+1:
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+ and t2, a1, t1
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+ not t3, t1
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+ and a1, a1, t3
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+ beqz t2, 2f
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+ /* CFLUSH.L2 rs1 = a1 */
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+ fence rw, rw
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+ .insn i 0x73, 0, x0, a1, -0x3C
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+ fence rw, rw
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+2:
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+ bge a0, a1, 4f
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+3:
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+ /* CDISCARD.L2 rs1 = a0 */
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+ fence rw, rw
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+ .insn i 0x73, 0, x0, a0, -0x3A
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+ fence rw, rw
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+ add a0, a0, t0
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+ blt a0, a1, 3b
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+4:
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+ ret
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+
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+ /*
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+ * __sbi_dubhe_L2_flush_range(start,len)
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+ *
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+ * Flush and invalidate the L2 cache within the specified region
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+ *
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+ * start - physical start address of region
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+ * len - size of memory region
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+ */
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+
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+ .align 3
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+ .global __sbi_dubhe_L2_flush_range
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+__sbi_dubhe_L2_flush_range:
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+ beqz a1, 2f
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+ li t0, DUBHE_L2_CACHELINE_SIZE
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+ addi t1, t0, -1
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+ add a1, a1, a0 /* Compute end address */
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+ not t2, t1
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+ and a0, a0, t2
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+1:
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+ /* CFLUSH.L2 rs1 = a0 */
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+ fence rw, rw
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+ .insn i 0x73, 0, x0, a0, -0x3C
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+ fence rw, rw
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+ add a0, a0, t0
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+ blt a0, a1, 1b
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+2:
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+ ret
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