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@@ -297,7 +297,7 @@ static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
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unsigned long mctr_inhbt;
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/* Make sure the counter index lies within the range and is not TM bit */
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- if (cidx > num_hw_ctrs || cidx == 1)
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+ if (cidx >= num_hw_ctrs || cidx == 1)
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return SBI_EINVAL;
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if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
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@@ -378,7 +378,7 @@ static int pmu_ctr_stop_hw(uint32_t cidx)
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mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
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/* Make sure the counter index lies within the range and is not TM bit */
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- if (cidx > num_hw_ctrs || cidx == 1)
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+ if (cidx >= num_hw_ctrs || cidx == 1)
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return SBI_EINVAL;
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if (!__test_bit(cidx, &mctr_inhbt)) {
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@@ -516,7 +516,7 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned lo
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u32 hartid = current_hartid();
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struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
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- if (cbase > num_hw_ctrs)
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+ if (cbase >= num_hw_ctrs)
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return SBI_EINVAL;
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/**
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@@ -593,8 +593,8 @@ static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, u32 hartid)
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int fw_base;
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unsigned long ctr_mask = cmask << cbase;
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- if (cbase <= num_hw_ctrs)
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- fw_base = num_hw_ctrs + 1;
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+ if (cbase < num_hw_ctrs)
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+ fw_base = num_hw_ctrs;
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else
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fw_base = cbase;
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@@ -694,7 +694,7 @@ int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info)
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return SBI_EINVAL;
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/* We have 31 HW counters with 31 being the last index(MHPMCOUNTER31) */
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- if (cidx <= num_hw_ctrs) {
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+ if (cidx < num_hw_ctrs) {
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cinfo.type = SBI_PMU_CTR_TYPE_HW;
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cinfo.csr = CSR_CYCLE + cidx;
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/* mcycle & minstret are always 64 bit */
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@@ -749,7 +749,7 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
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sbi_platform_pmu_init(plat);
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/* mcycle & minstret is available always */
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- num_hw_ctrs = sbi_hart_mhpm_count(scratch) + 2;
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+ num_hw_ctrs = sbi_hart_mhpm_count(scratch) + 3;
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total_ctrs = num_hw_ctrs + SBI_PMU_FW_CTR_MAX;
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}
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