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@@ -1,7 +1,7 @@
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OpenSBI SBI PMU extension support
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==================================
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SBI PMU extension supports allow supervisor software to configure/start/stop
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-any performance counter at anytime. Thus, an user can leverage full
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+any performance counter at anytime. Thus, a user can leverage full
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capability of performance analysis tools such as perf if SBI PMU extension is
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enabled. The OpenSBI implementation makes the following assumptions about the
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hardware platform.
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@@ -25,7 +25,7 @@ SBI PMU Device Tree Bindings
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----------------------------
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Platforms may choose to describe PMU event selector and event to counter mapping
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-values via device tree. The following sections describes the PMU DT node
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+values via device tree. The following sections describe the PMU DT node
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bindings in details.
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* **compatible** (Mandatory) - The compatible string of SBI PMU device tree node.
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@@ -42,7 +42,7 @@ This property shouldn't encode any raw hardware event.
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* **riscv,event-to-mhpmcounters**(Optional) - It represents a MANY-to-MANY
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mapping between a range of events and all the MHPMCOUNTERx in a bitmap format
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that can be used to monitor these range of events. The information is encoded in
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-a table format where each row represent a certain range of events and
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+a table format where each row represents a certain range of events and
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corresponding counters. The first column represents starting of the pmu event id
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and 2nd column represents the end of the pmu event id. The third column
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represent a bitmap of all the MHPMCOUNTERx. This property is mandatory if
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@@ -53,10 +53,10 @@ shouldn't encode any raw event.
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or MANY-to-MANY mapping between the raw event(s) and all the MHPMCOUNTERx in
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a bitmap format that can be used to monitor that raw event. The encoding of the
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raw events are platform specific. The information is encoded in a table format
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-where each row represent the specific raw event(s). The first column is a 64bit
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+where each row represents the specific raw event(s). The first column is a 64bit
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match value where the invariant bits of range of events are set. The second
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column is a 64 bit mask that will have all the variant bits of the range of
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-events cleared. Every other bits should be set in the mask.
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+events cleared. All other bits should be set in the mask.
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The third column is a 32bit value to represent bitmap of all MHPMCOUNTERx that
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can monitor these set of event(s).
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If a platform directly encodes each raw PMU event as a unique ID, the value of
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