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+OpenSBI SBI PMU extension support
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+==================================
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+SBI PMU extension supports allow supervisor software to configure/start/stop
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+any performance counter at anytime. Thus, an user can leverage full
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+capability of performance analysis tools such as perf if SBI PMU extension is
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+enabled. The OpenSBI implementation makes the following assumptions about the
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+hardware platform.
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+
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+ * MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, SBI PMU
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+extension will not be enabled.
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+
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+ * The platform must provide information about PMU event to counter mapping
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+via device tree or platform specific hooks. Otherwise, SBI PMU extension will
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+not be enabled.
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+
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+ * The platforms should provide information about the PMU event selector values
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+that should be encoded in the expected value of MHPMEVENTx while configuring
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+MHPMCOUNTERx for that specific event. This can be done via a device tree or
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+platform specific hooks. The exact value to be written to he MHPMEVENTx is
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+completely depends on platform. Generic platform writes the zero-extended event_idx
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+as the expected value for hardware cache/generic events as suggested by the SBI
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+specification.
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+
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+SBI PMU Device Tree Bindings
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+----------------------------
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+
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+Platforms may choose to describe PMU event selector and event to counter mapping
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+values via device tree. The following sections describes the PMU DT node
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+bindings in details.
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+
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+* **compatible** (Mandatory) - The compatible string of SBI PMU device tree node.
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+This DT property must have the value **riscv,pmu**.
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+
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+* **pmu,event-to-mhpmevent**(Optional) - It represents an ONE-to-ONE mapping
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+between a PMU event and the event selector value that platform expects to be
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+written to the MHPMEVENTx CSR for that event. The mapping is encoded in a
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+table format where each row represents an event. The first column represent the
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+event idx where the 2nd & 3rd column represent the event selector value that
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+should be encoded in the expected value to be written in MHPMEVENTx.
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+This property shouldn't encode any raw hardware event.
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+
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+* **pmu,event-to-mhpmcounters**(Optional) - It represents a MANY-to-MANY
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+mapping between a range of events and all the MHPMCOUNTERx in a bitmap format
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+that can be used to monitor these range of events. The information is encoded in
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+a table format where each row represent a certain range of events and
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+corresponding counters. The first column represents starting of the pmu event id
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+and 2nd column represents the end of the pmu event id. The third column
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+represent a bitmap of all the MHPMCOUNTERx. This property is mandatory if
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+event-to-mhpmevent is present. Otherwise, it can be omitted. This property
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+shouldn't encode any raw event.
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+
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+* **pmu,raw-event-to-mhpmcounters**(Optional) - It represents an ONE-to-MANY
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+mapping between a raw event and all the MHPMCOUNTERx in a bitmap format that can
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+be used to monitor that raw event. The information is encoded in a table format
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+where each raw represent a specific raw event. The first column stores the
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+expected event selector value that should be encoded in the expected value to be
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+written in MHPMEVENTx. The second column stores a bitmap of all the MHPMCOUNTERx
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+that can be used for monitoring the specified event.
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+
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+*Note:* A platform may choose to provide the mapping between event & counters
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+via platform hooks rather than the device tree.
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+
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+### Example
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+
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+```
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+pmu {
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+ compatible = "riscv,pmu";
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+ interrupts = <0x100>;
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+ interrupt-parent = <&plic>
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+ pmu,event-to-mhpmevent = <0x0000B 0x0000 0x0001>,
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+ pmu,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
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+ <0x00002 0x00002 0x00000004>,
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+ <0x00003 0x0000A 0x00000ff8>,
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+ <0x10000 0x10033 0x000ff000>,
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+ pmu,raw-event-to-mhpmcounters = <0x0000 0x0002 0x00000f8>,
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+ <0x0000 0x0003 0x00000ff0>,
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+};
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+
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+```
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