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@@ -39,6 +39,33 @@ _start:
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csrr a6, CSR_MHARTID
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blt zero, a6, _wait_for_boot_hart
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+ /* Save load address */
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+ la t0, _load_start
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+ la t1, _start
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+ REG_S t1, 0(t0)
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+
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+ /* Relocate if load address != link address */
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+ la t0, _link_start
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+ REG_L t0, 0(t0)
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+ la t1, _link_end
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+ REG_L t1, 0(t1)
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+ la t2, _load_start
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+ REG_L t2, 0(t2)
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+ beq t0, t2, _relocate_done
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+ la t4, _relocate_done
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+ sub t4, t4, t2
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+ add t4, t4, t0
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+_relocate_copy:
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+ REG_L t3, 0(t2)
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+ REG_S t3, 0(t0)
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+ add t0, t0, __SIZEOF_POINTER__
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+ add t2, t2, __SIZEOF_POINTER__
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+ blt t0, t1, _relocate_copy
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+ jr t4
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+_relocate_done:
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+
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+ /* At this point we are running from link address */
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+
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/* Reset all registers for boot HART */
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li ra, 0
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call _reset_regs
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@@ -209,18 +236,29 @@ _fdt_reloc_done:
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/* Update boot hart flag */
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la a4, _boot_hart_done
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- li a5, 1
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+ la a5, _start_warm
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REG_S a5, (a4)
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+ fence rw, rw
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+ la t0, _link_start
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+ REG_L t0, 0(t0)
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+ sub a4, a4, t0
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+ la t0, _load_start
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+ REG_L t0, 0(t0)
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+ add a4, a4, t0
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+ REG_S a5, (a4)
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+ fence rw, rw
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+ j _start_warm
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/* Wait for boot hart */
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_wait_for_boot_hart:
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la a4, _boot_hart_done
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- REG_L a5, (a4)
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+ REG_L a5, 0(a4)
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/* Reduce the bus traffic so that boot hart may proceed faster */
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nop
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nop
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nop
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beqz a5, _wait_for_boot_hart
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+ jr a5
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_start_warm:
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/* Reset all registers for non-boot HARTs */
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@@ -263,11 +301,9 @@ _start_warm:
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la a4, _trap_handler
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csrw CSR_MTVEC, a4
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/* Make sure that mtvec is updated */
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- 1:
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- csrr a5, CSR_MTVEC
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+1: csrr a5, CSR_MTVEC
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bne a4, a5, 1b
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-
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/* Initialize SBI runtime */
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csrr a0, CSR_MSCRATCH
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call sbi_init
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@@ -276,9 +312,14 @@ _start_warm:
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j _start_hang
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.align 3
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- .section .data, "aw"
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_boot_hart_done:
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RISCV_PTR 0
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+_load_start:
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+ RISCV_PTR _fw_start
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+_link_start:
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+ RISCV_PTR _fw_start
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+_link_end:
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+ RISCV_PTR _fw_reloc_end
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.align 3
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.section .entry, "ax", %progbits
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